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  • DRV8304 38-V 3-Phase Smart Gate Driver

    • SLVSE39B November   2017  – July 2018 DRV8304

      UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  • CONTENTS
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  • DRV8304 38-V 3-Phase Smart Gate Driver
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 3-Phase Smart Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 7.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 7.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. 7.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. 7.3.1.2 Device Interface Modes
          1. 7.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 7.3.1.2.2 Hardware Interface
        3. 7.3.1.3 Gate Driver Voltage Supplies
        4. 7.3.1.4 Smart Gate-Drive Architecture
          1. 7.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 7.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 7.3.1.4.3 Gate Drive Clamp
          4. 7.3.1.4.4 Propagation Delay
          5. 7.3.1.4.5 MOSFET VDS Monitors
          6. 7.3.1.4.6 VDRAIN Sense Pin
      2. 7.3.2 DVDD Linear Voltage Regulator
      3. 7.3.3 Pin Diagrams
      4. 7.3.4 Low-Side Current-Shunt Amplifiers
        1. 7.3.4.1 Bidirectional Current Sense Operation
        2. 7.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 7.3.4.3 Offset Calibration
      5. 7.3.5 Gate-Driver Protection Circuits
        1. 7.3.5.1 VM Supply Undervoltage Lockout (UVLO)
        2. 7.3.5.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
        3. 7.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 7.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 7.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 7.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 7.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
          1. 7.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 7.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 7.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. 7.3.5.5 Gate Driver Fault (GDF)
        6. 7.3.5.6 Thermal Warning (OTW)
        7. 7.3.5.7 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
          1. 7.5.1.1.1 SPI Format
    6. 7.6 Register Maps
      1. Table 1. DRV8304S Register Map
      2. 7.6.1    Status Registers (DRV8304S Only)
        1. 7.6.1.1 Fault Status Register 1 (Address = 0x00) [reset = 0x00]
          1. Table 11. Fault Status Register 1 Field Descriptions
        2. 7.6.1.2 Fault Status Register 2 (Address = 0x01) [reset = 0x00]
          1. Table 12. Fault Status Register 2 Field Descriptions
      3. 7.6.2    Control Registers (DRV8304S Only)
        1. 7.6.2.1 Driver Control Register (Address = 0x02) [reset = 0x00]
          1. Table 14. Driver Control Field Descriptions
        2. 7.6.2.2 Gate Drive HS Register (Address = 0x03) [reset = 0x377]
          1. Table 15. Gate Drive HS Field Descriptions
        3. 7.6.2.3 Gate Drive LS Register (Address = 0x04) [reset = 0x777]
          1. Table 16. Gate Drive LS Register Field Descriptions
        4. 7.6.2.4 OCP Control Register (Address = 0x05) [reset = 0x145]
          1. Table 17. OCP Control Field Descriptions
        5. 7.6.2.5 CSA Control Register (Address = 0x06) [reset = 0x283]
          1. Table 18. CSA Control Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Primary Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External MOSFET Support
            1. 8.2.1.2.1.1 Example
          2. 8.2.1.2.2 IDRIVE Configuration
            1. 8.2.1.2.2.1 Example
          3. 8.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 8.2.1.2.3.1 Example
          4. 8.2.1.2.4 Sense-Amplifier Bidirectional Configuration
            1. 8.2.1.2.4.1 Example
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Sense-Amplifier Unidirectional Configuration
            1. 8.2.2.2.1.1 Example
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
  • RHA|40
    • QFND227K
Orderable Information
  • slvse39b_oa
  • slvse39b_pm
search No matches found.
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    • Expanded reading width
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DATA SHEET

DRV8304 38-V 3-Phase Smart Gate Driver

1 Features

  • 6-V to 38-V, Triple Half-Bridge Gate Driver With Integrated 3x Current Sense Amplifiers (CSA)
    • 40-V Absolute Maximum Rating
    • Fully Optimized for 12-V and 24-V DC Rails
    • Drives High-Side and Low-Side N-Channel MOSFETs
    • Supports 100% PWM Duty Cycle
  • Smart Gate-Drive Architecture
    • Adjustable Slew-Rate Control for Better EMI and EMC Performance
    • VGS Hand-Shake and Minimum Dead-Time Insertion to Avoid Shoot-Through
    • 15-mA to 150-mA Peak Source Current
    • 30-mA to 300-mA Peak Sink Current
  • 6x, 3x, 1x and Independent PWM Modes
    • Supports 120º Sensored Operation
  • Integrated Gate-Driver Power Supplies
    • High-Side Doubler Charge Pump
    • Low-Side Linear Regulator
  • Integrated Triple Current-Shunt Amplifiers
    • Adjustable Gain (5, 10, 20, 40 V/V)
    • Bidirectional or Unidirectional Support
  • SPI or Hardware Device Variants
  • Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
  • Low-Power Sleep Mode
  • Linear Voltage Regulator, 3.3-V, 30-mA
  • Integrated Protection Features
    • VM Undervoltage Lockout (UVLO)
    • Charge Pump Undervoltage (CPUV)
    • MOSFET VDS Overcurrent Protection (OCP)
    • MOSFET Shoot-Through Protection
    • Gate Driver Fault (GDF)
    • Thermal Warning and Shutdown (OTW/OTSD)
    • Fault Condition Indicator (nFAULT)

2 Applications

  • Printers
  • BLDC Motor Modules
  • White Goods
  • CPAPs, Fans, and Pumps
  • Drones, Robotics, and RC Toys
  • ATM and Currency Counting

3 Description

The DRV8304 device is an integrated gate driver for 3-phase brushless DC (BLDC) motors applications for 12-V and 24-V DC rails. These applications include field-oriented control (FOC), sinusoidal current control, and trapezoidal current control of BLDC motors. The device integrates three current-sense amplifiers (CSA) for sensing the phase currents of BLDC motors for optimum FOC and current-control system implementation. An AUTOCAL feature automatically calibrates the CSA offset error for accurate current sensing.

The device is based on smart gate-drive (SGD) architecture to eliminate the need of any external gate components (resistors and Zener diodes) while fully protecting the external FETs. The SGD architecture optimizes dead time to avoid any shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by gate slew-rate control, and protects against any gate-short conditions through VGS hand-shaking and dead time insertion. Strong pulldown current also prevents any dv/dt gate turnon.

Various PWM control modes (1x, 3x, 6x, and independent) are supported for simple interfacing to control circuits that can be powered by the 30-mA, 3.3-V internal regulator. These modes decrease the number of output peripherals of the controller for the specific motor-control requirements and provide flexibility of control. The device also has a 1x mode for sensored trapezoidal control of the BLDC motor by using the internal block-commutation table. The device can also be configured to drive multiple loads, such as solenoids, in independent mode.

Device Information(1)

PART NUMBER PACKAGE INTERFACE
DRV8304 VQFN (40) Hardware
SPI
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

DRV8304 drv8304_simplified_schematic.gif

4 Revision History

Changes from A Revision (June 2018) to B Revision

  • Deleted preview status from the SPI version of the deviceGo

Changes from * Revision (November 2017) to A Revision

  • Changed the data sheet from Advance Information to Production DataGo

5 Pin Configuration and Functions

DRV8304H RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View
DRV8304S RHA Package
40-Pin VQFN With Exposed Thermal Pad
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
DRV8304H DRV8304S
AGND 32 32 PWR Device analog ground. Connect to system ground.
CAL 31 31 I Amplifier calibration input. Set logic high to internally short amplifier inputs and perform offset calibration.
CPH 2 2 PWR Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
CPL 1 1 PWR Charge pump switching node. Connect a X5R or X7R, 22-nF, VM-rated ceramic capacitor between the CPH and CPL pins.
DVDD 33 33 PWR 3.3-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and AGND pins. This regulator can source up to 30 mA externally.
ENABLE 30 30 I Gate driver enable. When this pin is logic low the device enters a low power sleep mode. An 5 to 32-µs low pulse can be used to reset fault conditions.
GAIN 29 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 27 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver (GHA).
INHB 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver (GHB).
INHC 38 38 I High-side gate driver control input. This pin controls the output of the high-side gate driver (GHC).
INLA 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver (GLA).
INLB 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver (GLB).
INLC 39 39 I Low-side gate driver control input. This pin controls the output of the low-side gate driver (GLC).
MODE 26 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 25 25 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 29 I Serial chip select. A logic low on this pin enables serial interface communication.
PGND 40 40 PWR Device power ground. Connect to system ground.
SCLK — 28 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 27 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 26 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 7 7 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 17 17 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 10 10 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB 11 11 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC 20 20 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA 23 23 O Shunt amplifier output.
SOB 22 22 O Shunt amplifier output.
SOC 21 21 O Shunt amplifier output.
SPA 9 9 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPB 12 12 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
SPC 19 19 I Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor.
VCP 3 3 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VDRAIN 5 5 I High-side MOSFET drain sense input. Connect to the common point of the external MOSFET drains.
VDS 28 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VM 4 4 PWR Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater than or equal to 10-uF local capacitance between the VM and PGND pins.
VREF 24 24 PWR Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-μF, 6.3-V ceramic capacitor between the VREF and AGND pins.
(1) PWR = power, I = input, O = output, OD = open-drain

 
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