SLVSE39B November   2017  – July 2018 DRV8304

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 3-Phase Smart Gate Drivers
        1. 7.3.1.1 PWM Control Modes
          1. 7.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
          2. 7.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)
          3. 7.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)
          4. 7.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
        2. 7.3.1.2 Device Interface Modes
          1. 7.3.1.2.1 Serial Peripheral Interface (SPI)
          2. 7.3.1.2.2 Hardware Interface
        3. 7.3.1.3 Gate Driver Voltage Supplies
        4. 7.3.1.4 Smart Gate-Drive Architecture
          1. 7.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control
          2. 7.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
          3. 7.3.1.4.3 Gate Drive Clamp
          4. 7.3.1.4.4 Propagation Delay
          5. 7.3.1.4.5 MOSFET VDS Monitors
          6. 7.3.1.4.6 VDRAIN Sense Pin
      2. 7.3.2 DVDD Linear Voltage Regulator
      3. 7.3.3 Pin Diagrams
      4. 7.3.4 Low-Side Current-Shunt Amplifiers
        1. 7.3.4.1 Bidirectional Current Sense Operation
        2. 7.3.4.2 Unidirectional Current Sense Operation (SPI only)
        3. 7.3.4.3 Offset Calibration
      5. 7.3.5 Gate-Driver Protection Circuits
        1. 7.3.5.1 VM Supply Undervoltage Lockout (UVLO)
        2. 7.3.5.2 VCP Charge-Pump Undervoltage Lockout (CPUV)
        3. 7.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
          1. 7.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
          3. 7.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
          4. 7.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
        4. 7.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
          1. 7.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
          3. 7.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
          4. 7.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
        5. 7.3.5.5 Gate Driver Fault (GDF)
        6. 7.3.5.6 Thermal Warning (OTW)
        7. 7.3.5.7 Thermal Shutdown (OTSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Gate Driver Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 SPI
          1. 7.5.1.1.1 SPI Format
    6. 7.6 Register Maps
      1. Table 1. DRV8304S Register Map
      2. 7.6.1    Status Registers (DRV8304S Only)
        1. 7.6.1.1 Fault Status Register 1 (Address = 0x00) [reset = 0x00]
          1. Table 11. Fault Status Register 1 Field Descriptions
        2. 7.6.1.2 Fault Status Register 2 (Address = 0x01) [reset = 0x00]
          1. Table 12. Fault Status Register 2 Field Descriptions
      3. 7.6.2    Control Registers (DRV8304S Only)
        1. 7.6.2.1 Driver Control Register (Address = 0x02) [reset = 0x00]
          1. Table 14. Driver Control Field Descriptions
        2. 7.6.2.2 Gate Drive HS Register (Address = 0x03) [reset = 0x377]
          1. Table 15. Gate Drive HS Field Descriptions
        3. 7.6.2.3 Gate Drive LS Register (Address = 0x04) [reset = 0x777]
          1. Table 16. Gate Drive LS Register Field Descriptions
        4. 7.6.2.4 OCP Control Register (Address = 0x05) [reset = 0x145]
          1. Table 17. OCP Control Field Descriptions
        5. 7.6.2.5 CSA Control Register (Address = 0x06) [reset = 0x283]
          1. Table 18. CSA Control Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Primary Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External MOSFET Support
            1. 8.2.1.2.1.1 Example
          2. 8.2.1.2.2 IDRIVE Configuration
            1. 8.2.1.2.2.1 Example
          3. 8.2.1.2.3 VDS Overcurrent Monitor Configuration
            1. 8.2.1.2.3.1 Example
          4. 8.2.1.2.4 Sense-Amplifier Bidirectional Configuration
            1. 8.2.1.2.4.1 Example
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternative Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Sense-Amplifier Unidirectional Configuration
            1. 8.2.2.2.1.1 Example
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHA|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at VVM = 6 to 38 V over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (DVDD, VM)
IVM VM operating supply current ENABLE = 1; INHX = 0 V; INLX = 0 V 5 7 mA
IVMQ VM sleep mode supply current ENABLE = 0; VVM = 24 V; TA = 25°C 20 40 µA
ENABLE = 0, VVM = 24 V, TA = 125°C (1) 100 µA
tRST Reset pulse time ENABLE = 0 V period to reset faults 15 40 µs
tSLEEP Sleep time ENABLE = 0 V to driver tri-stated 200 µs
tWAKE Wake-up time VVM > VUVLO; ENABLE = 3.3 V to output transition 1 ms
VDVDD Internal logic regulator voltage IDVDD = 0 to 30 mA 2.9 3.3 3.6 V
CHARGE PUMP (CPH, CPL, VCP)
VVCP VCP operating voltage with respect to VM VM = 12 to 38 V; IVCP = 0 to 15 mA 7 10 11.5 V
VM = 10 V; IVCP = 0 to 10 mA 6.5 7.5 9.5 V
VM = 8 V; IVCP = 0 to 5 mA 5 6 7.5 V
VM = 6 V; IVCP = 0 to 1 mA 3.8 4.3 6.5 V
LOGIC-LEVEL INPUTS (CAL, INHX, INLX, SCLK, SDI, nSCS)
VIL Input logic low voltage 0 0.8 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –1 1 µA
IIH Input logic high current VPIN (Pin Voltage) = 5 V 100 µA
RPD Pulldown Resistance to AGND (CAL, INHX, INLX, SCLK, SDI, nSCS) 100 kΩ
LOGIC-LEVEL INPUTS (ENABLE)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –10 10 µA
IIH Input logic high current VPIN (Pin Voltage) = 5 V -5 5 µA
FOUR-LEVEL INPUTS (GAIN, MODE)
VI1 Input mode 1 voltage Tied to AGND 0 V
VI2 Input mode 2 voltage 45 kΩ ± 5% to AGND 1.2 V
VI3 Input mode 3 voltage Hi-Z 2 V
VI4 Input mode 4 voltage Tied to DVDD 3.3 V
SEVEN-LEVEL INPUTS (IDRIVE, VDS)
VI1 Input mode 1 voltage Tied to AGND 0 V
VI2 Input mode 2 voltage 18 kΩ ± 5% to AGND 0.5 V
VI3 Input mode 3 voltage 75 kΩ ± 5% to AGND 1.1 V
VI4 Input mode 4 voltage Hi-Z 1.65 V
VI5 Input mode 5 voltage 75 kΩ ± 5% to DVDD 2.2 V
VI6 Input mode 6 voltage 18 kΩ ± 5% to DVDD 2.8 V
VI7 Input mode 7 voltage Tied to DVDD 3.3 V
OPEN-DRAIN OUTPUTS (nFAULT, SDO)
VOL Output logic low voltage IOD = 2 mA 0.1 V
IOZ Output logic high current VOD = 5 V –1 1 µA
GATE DRIVERS (GHX, GLX, SHX)
VGHS(1) High-side VGS gate drive (gate-to-source) VVM = 12 to 38 V; IHS_GATE = 0 to 15 mA 7 10 11.5 V
VVM = 10 V; IHS_GATE = 0 to 10 mA 6.5 7.5 8.5
VVM = 8 V; IHS_GATE = 0 to 5 mA 5 6 7
VVM = 6 V; IHS_GATE = 0 to 1 mA 3.8 4.3 6.5
VGSL(1) Low-side VGS gate drive (gate-to-source) VVM = 12 to 38 V; ILS_GATE = 0 to 15 mA 7.5 10 12.5 V
VVM = 10 V; ILS_GATE = 0 to 10 mA 5.5 7.5 9.5
VVM = 8 V; ILS_GATE = 0 to 5 mA 3.5 6 8.5
VVM = 6 V; ILS_GATE = 0 to 1 mA 3 4.3 6.5
tDEAD Output dead time (SPI Device) DEAD_TIME = 00b 40 ns
DEAD_TIME = 01b 120
DEAD_TIME = 10b 200
DEAD_TIME = 11b 400
tDEAD Output dead time (HW Device) 120 ns
tDRIVE Peak gate drive time (SPI Device) TDRIVE = 00b 500 ns
TDRIVE = 01b 1000
TDRIVE = 10b 2000
TDRIVE = 11b 4000
tDRIVE Peak gate drive time (HW Device) 4000 ns
IDRIVEP Peak source gate current (high-side and low-side) (SPI Device) IDRIVEP_HS or IDRIVEP__LS = 000b 15 mA
IDRIVEP_HS or IDRIVEP__LS = 001b 15
IDRIVEP_HS or IDRIVEP__LS = 010b 45
IDRIVEP_HS or IDRIVEP__LS = 011b 60
IDRIVEP_HS or IDRIVEP__LS = 100b 90
IDRIVEP_HS or IDRIVEP__LS = 101b 105
IDRIVEP_HS or IDRIVEP__LS = 110b 135
IDRIVEP_HS or IDRIVEP__LS = 111b 150
IDRIVEP Peak source gate current (high-side and low-side) (HW Device) IDRIVE tied to AGND 15 mA
IDRIVE 18 kΩ (±5%) to AGND 45
IDRIVE 75 kΩ (±5%) to AGND 60
IDRIVE Hi-Z ( > 500 kΩ to AGND) 90
IDRIVE 75 kΩ (±5%) to DVDD 105
IDRIVE 18 kΩ (±5%) to DVDD 135
IDRIVE tied to DVDD 150
IDRIVEN Peak sink gate current (high-side and low-side) (SPI Device) IDRIVEN_HS or IDRIVEN_LS = 000b 30 mA
IDRIVEN_HS or IDRIVEN_LS = 001b 30
IDRIVEN_HS or IDRIVEN_LS = 010b 90
IDRIVEN_HS or IDRIVEN_LS = 011b 120
IDRIVEN_HS or IDRIVEN_LS = 100b 180
IDRIVEN_HS or IDRIVEN_LS = 101b 210
IDRIVEN_HS or IDRIVEN_LS = 110b 270
IDRIVEN_HS or IDRIVEN_LS = 111b 300
IDRIVEN Peak sink gate current (high-side and low-side) (HW Device) IDRIVE tied to AGND 30 mA
IDRIVE 18 kΩ (±5%) to AGND 90
IDRIVE 75 kΩ (±5%) to AGND 120
IDRIVE Hi-Z ( > 500 kΩ to AGND) 180
IDRIVE 75 kΩ (±5%) to DVDD 210
IDRIVE 18 kΩ (±5%) to DVDD 270
IDRIVE tied to DVDD 300
IHOLD FET holding current Source current after tDRIVE 15 mA
Sink current after tDRIVE 30
ISTRONG FET hold-off strong pulldown GLX pull-down current during GHX tDRIVE period or vice-versa  300 mA
ROFF FET gate hold-off resistor GHX to SHX and GLX to PGND 150 kΩ
tPD Propagation delay INHX/INLX tansition to GHX/GLX transition   180 250 ns
CURRENT SHUNT AMPLIFIERS (SNx, SOx, SPx, VREF)
GCSA Amplifier gain (SPI Device) CSA_GAIN = 00b, VREF = 3.3 to 5 V 4.85 5 5.15 V/V
CSA_GAIN = 01b, VREF = 3.3 to 5 V 9.7 10 10.3
CSA_GAIN = 10b, VREF = 3.3 to 5 V 19.4 20 20.6
CSA_GAIN = 11b, VREF = 3.3 to 5 V 38.8 40 41.2
GCSA Amplifier gain (HW Device) Tied to AGND, VREF = 3.3 to 5 V 4.85 5 5.15 V/V
45 kΩ ± 5% to AGND, VREF = 3.3 to 5 V 9.7 10 10.3
Hi-Z, VREF = 3.3 to 5 V 19.4 20 20.6
Tied to DVDD, VREF = 3.3 to 5 V 38.8 40 41.2
tSET(1) Settling time to ±1%, 30 pF STEP on SOX = 0.5 V; GCSA = 5 V/V, VREF = 3.3 to 5 V 260 ns
STEP on SOX = 0.5 V; GCSA = 10 V/V, VREF = 3.3 to 5 V 400
STEP on SOX = 0.5 V; GCSA = 20 V/V, VREF = 3.3 to 5 V 700
STEP on SOX = 0.5 V; GCSA = 40 V/V, VREF = 3.3 to 5 V 1550
VSP, COM(1) Common-mode input range –0.5 0.5 V
VOFF Input offset error VSP = VSN = 0 V, GCSA = 5, VREF = 3.3 V ± 10% –5 5 mV
VSP = VSN = 0 V, GCSA = 10, VREF = 3.3 V ± 10% –2.5 2.5 mV
VSP = VSN = 0 V, GCSA = 20, VREF = 3.3 V ± 10% –1.5 1.5 mV
VSP = VSN = 0 V, GCSA = 40, VREF = 3.3 V ± 10% –1.25 1.25 mV
VSP = VSN = 0 V, GCSA = 5, VREF = 5 V ± 10% –7 7 mV
VSP = VSN = 0 V, GCSA = 10, VREF = 5 V ± 10% –3.5 3.5 mV
VSP = VSN = 0 V, GCSA = 20, VREF = 5 V ± 10% –2.25 2.25 mV
VSP = VSN = 0 V, GCSA = 40, VREF = 5 V ± 10% –1.5 1.5 mV
VDRIFT(1) Drift offset VSP = VSN = 0 V 10 µV/°C
VLINEAR(1) SOX output voltage linear range 0.25 VVREF – 0.25 V
VBIAS SOX output voltage bias (SPI Device) VSP = VSN = 0 V, VREF_DIV = 0b VVREF – 0.3 V
VSP = VSN = 0 V, VREF_DIV = 1b VVREF/2
VBIAS SOX output voltage bias (HW Device) VSP = VSN = 0 V VVREF/2 V
IBIAS SPX/SNX negative input bias current VSP = VSN = 0 V 200 µA
VREFUV VREF undervoltage 2.6 V
IVREF VREF input current VREF = 5.0 V 1 2 mA
PROTECTION CIRCUITS
VUVLO VM undervoltage lockout VM falling, UVLO report 5.4 5.8 V
VM rising, UVLO recovery 5.6 6
VUVLO_HYS VM undervoltage hysteresis Rising to falling threshold 200 mV
tUVLO_DEG(1) VM undervoltage deglitch time VM falling, UVLO report 10 µs
VCPUV Charge pump undervoltage With respect to VM 2.4 V
VGS_CLAMP Gate drive clamping voltage Positive clamping voltage 10.5 15 V
Negative clamping voltage –0.6
VDS_OCP VDS overcurrent trip voltage (SPI Device) VDS_LVL = 000b 0.15 V
VDS_LVL = 001b 0.24
VDS_LVL = 010b 0.4
VDS_LVL = 011b 0.51
VDS_LVL = 100b 0.6
VDS_LVL = 101b 0.9
VDS_LVL = 110b 1.8
VDS_LVL = 111b Disabled
VDS_OCP VDS overcurrent trip voltage (HW Device) VDS tied to AGND 0.15 V
VDS 18 kΩ (±5%) to AGND 0.24
VDS 75 kΩ (±5%) to AGND 0.4
VDS Hi-Z ( > 500 kΩ to AGND) 0.6
VDS 75 kΩ (±5%) to DVDD 0.9
VDS 18 kΩ (±5%) to DVDD 1.8
VDS tied to DVDD Disabled
VSEN_OCP VSENSE overcurrent trip voltage (SPI Device) SEN_LVL = 00b 0.25 V
SEN_LVL = 01b 0.5
SEN_LVL = 10b 0.75
SEN_LVL = 11b 1
VSEN_OCP VSENSE overcurrent trip voltage (HW Device) 1 V
tOCP_DEG VDS and VSENSE overcurrent deglitch time 4.5 µs
tRETRY Overcurrent retry time (SPI Device) TRETRY = 0b 4 ms
TRETRY = 1b 500 µs
tRETRY Overcurrent retry time (HW Device) 4 ms
TOTW(1) Thermal warning temperature Die temperature (Tj) 120 140 °C
TOTSD(1) Thermal shutdown temperature Die temperature (Tj) 150 170 °C
THYS(1) Thermal hysteresis Die temperature (Tj) 20 °C
(1) Specified by design and characterization data