SLVSE39B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
This section applies only to the DRV8304 SPI device.
NOTE
Do not modify reserved registers or addresses not listed in the register map (Table 1). Writing to these registers may have unintended effects. For all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller, set the LOCK bits to lock the SPI registers.
Name | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Type | Address |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Fault Status 1 | FAULT | VDS_OCP | GDF | UVLO | OTSD | VDS_HA | VDS_LA | VDS_HB | VDS_LB | VDS_HC | VDS_LC | R | 0h |
VGS Status 2 | SA_OC | SB_OC | SC_OC | OTW | CPUV | VGS_HA | VGS_LA | VGS_HB | VGS_LB | VGS_HC | VGS_LC | R | 1h |
Driver Control | Reserved | DIS_CPUV | DIS_GDF | OTW_REP | PWM_MODE | 1PWM_COM | 1PWM_DIR | COAST | BRAKE | CLR_FLT | RW | 2h | |
Gate Drive HS | LOCK | Reserved | IDRIVEP_HS | Reserved | IDRIVEN_HS | RW | 3h | ||||||
Gate Drive LS | CBC | TDRIVE | Reserved | IDRIVEP_LS | Reserved | IDRIVEN_LS | RW | 4h | |||||
OCP Control | TRETRY | DEAD_TIME | OCP_MODE | OCP_ACT | Reserved | VDS_LVL | RW | 5h | |||||
CSA Control | Reserved | VREF_DIV | LS_REF | CSA_GAIN | DIS_SEN | SPI_CAL | AUTOCAL | Reserved | SEN_LVL | RW | 6h | ||
Reserved | Reserved | RW | 7h |