SLVSE39B November 2017 – July 2018 DRV8304
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low. The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).