Table 3. 1-PWM Active Freewheeling

Table 4. 1-PWM Diode Freewheeling

7.3.5.1 IDRIVE: Gate Driver Output Current

The first component of the gate drive architecture implements adjustable current control for the gates of the external power MOSFETs. This feature allows the gate driver to control the V_DS slew rate of the MOSFETs by adjusting the gate drive current. This is realized internally to reduce the need for external components inline with the gates of the MOSFETs. The DRV8305 provides 12 adjustable source and sink current levels for the high-side (the high sides of all three phases share the same setting) and low-side gate drivers (the low sides of all three phases share the same settings). The gate drive levels are adjustable through the SPI registers in both the standby and operating states. This flexibility allows the system designer to tune the performance of the driver for different operating conditions through software alone.

The gate drivers are implemented as temperature compensated, constant current sources up to the 80 mA (sink)/70 mA (source) current settings in order to maintain the accuracy required for precise slew rate control. The current source architecture helps eliminate the temperature, process, and load-dependent variation associated with internal and external series limiting resistors. Beyond that, internal switches are adjusted to create the desired settings up to the 1.25 A (sink)/1 A (source) settings. For higher currents, internal series switches are used to minimize the power losses associated with mirroring such large currents.

Control of the gate current during the MOSFET Miller region is a key component for adjusting the MOSFET V_DS rise and fall times. MOSFET V_DS slew rates are a critical parameter for optimizing emitted radiations, energy and duration of diode recovery spikes, dV/dt related turn on leading to shoot-through, and voltage transients related to parasitics.

When a MOSFET is enhanced, three different charges must be supplied to the MOSFET gate. The MOSFET drain to source voltage will slew primarily during the Miller region. By controlling the rate of charge to the MOSFET gate (gate drive current strength) during the Miller region, it is possible to optimize the VDS slew rate for the reasons mentioned.

1. Q_GS = Gate-to-source charge
2. Q_GD = Gate-to-drain charge (Miller charge)
3. Remaining Q_G

Figure 10. MOSFET Charge Example

7.3.5.2 TDRIVE: Gate Driver State Machine

The DRV8305 gate driver uses an integrated state machine (TDRIVE) in the gate driver to protect against excessive current on the gate drive outputs, shoot-through in the external MOSFET, and dV/dt turn on due to switching on the phase nodes. The TDRIVE state machine allows for the design of a robust and efficient motor drive system with minimal overhead.

The state machine incorporates internal handshaking when switching from the low to the high-side external MOSFET or vice-versa. The handshaking is designed to prevent the external MOSFETs from entering a period of cross conduction, also known as shoot-through. The internal handshaking uses the V_GS monitors of the DRV8305 to determine when one MOSFET has been disabled and the other can be enabled. This allows the gate driver to insert an optimized dead time into the system without the risk of cross conduction. Any deadtime added externally through the MCU or SPI register will be inserted after the handshake process.

The state machine also incorporates a gate drive timer to ensure that under abnormal circumstances such as a short on the MOSFET gate or the inadvertent turn on of a MOSFET V_GS clamp, the high peak current through the DRV8305 and MOSFET is limited to a fixed duration. This concept is visualized in the figure below. First, the DRV8305 receives a command to enable or disable the MOSFET through INHx or INLx inputs. Second, the gate driver is enabled and a strong current is applied to the MOSFET gate and the gate voltage begins to change. If the gate voltage has not changed to the desired level after the t_DRIVE period (indicating a short circuit or overcurrent condition on the MOSFET gate), the DRV8305 signals a gate drive fault and the gate drive is disabled to help protect the external MOSFET and DRV8305. If the MOSFET does successfully enable or disable, after the t_DRIVE period the DRV8305 will enable a lower hold current to ensure the MOSFET remains enabled or disabled and improve efficiency of the gate drive.

Select a t_DRIVE time that is longer than the time needed to charge or discharge the gate capacitances of the external MOSFETs. The TDRIVE SPI registers should be configured so that the MOSFET gates are charged completely within t_DRIVE during normal operation. If t_DRIVE is too low for a given MOSFET, then the MOSFET may not turn on completely. It is suggested to tune these values in-system with the required external MOSFETs to determine the best possible setting for the application. A good starting value is a t_DRIVE period that is 2x the expected rise or fall times of the external MOSFET gates. Note that TDRIVE will not increase the PWM time and will simply terminate if a PWM command is received while it is active.

Figure 11. TDRIVE Gate Drive State Machine

7.3.5.3 CSAs: Current Shunt Amplifiers

The DRV8305 includes three high performance low-side current shunt amplifiers for accurate current measurement utilizing low-side shunt resistors in the external half-bridges. They are commonly used to measure the motor phase current to implement overcurrent protection, external torque control, or external commutation control through the application MCU.

The current shunt amplifiers have the following features:

• Each of the three current sense amplifiers can be programmed and calibrated independently.
• Can provide output bias up to 2.5 V to support bidirectional current sensing.
• May be used for either individual or total current shunt sensing.
• Four programmable gain settings through SPI registers (10, 20, 40 and 80 V/V).
• Reference voltage for output bias provided from voltage regulator VREG for DRV83053Q and DRV83055Q
• Reference voltage for output bias provided from externally applied voltage on VREG pin for DRV8305NQ and DRV8305NE
• Programmable output bias scaling. The scaling factor k can be programmed through SPI registers (1/2 or 1/4)
• Programmable blanking time (delay) of the amplifier outputs. The blanking time is implemented from any rising or falling edge of gate drive outputs. The blanking time is applied to all three current sense amplifiers equally. In case the current sense amplifiers are already being blanked when another gate driver rising or falling edge is seen, the blanking interval will be restarted at the edge. Note that the blanking time options do not include delay from internal amplifier loading or delays from the trace or component loads on the amplifier output. The programmable blanking time may be overridden to have no delay (default value).
• Minimize DC offset and drift through temperature with DC calibrating through SPI register. When DC calibration is enabled, device will short input of current shunt amplifier and disconnect the load. DC calibrating can be done at anytime, even when the MOSFET is switching because the load is disconnected. For best result, perform the DC calibrating during switching off period when no load is present to reduce the potential noise impact to the amplifier.

The output of current shunt amplifier can be calculated as:

Equation 1.

where

• VREF is the reference voltage from the VREG pin.
• G is the gain setting of the amplifier.
• k = 2 or 4
• SNx and SPx are the inputs of channel x.
• SPx should connect to the low-side (ground) of the sense resistor for the best common mode rejection.
• SNx should connect to the high-side (LS MOSFET source) of the sense resistor.

Figure 12 shows current amplifier simplified block diagram.

Figure 12. Current Shunt Amplifier Simplified Block Diagram

7.3.8.1 Fault and Warning Classification

The DRV8305 integrates extensive error detection and monitoring features. These features allow the design of a robust system that can protect against a variety of system related failure modes. The DRV8305 classifies error events into two categories and takes different device actions dependent on the error classification.

The first error class is a Warning. There are several types of conditions that are classified as warning only. Warning errors are report only and the DRV8305 will take no other action effecting the gate drivers or other blocks. When a warning condition occurs it will be reported in the corresponding SPI status register bit and on the nFAULT pin with a repeating 56 µs pulse low followed by a 56 µs pulse high. A warning error can be cleared by an SPI read to the corresponding status register bit. The same warning will not be reported through the nFAULT pin again unless that warning or condition passes and then reoccurs.

• A warning error is reported on the nFAULT pin with a repeating 56 µs pulse low followed by a 56 µs pulse high
• The warning is reported on the nFAULT pin until a SPI read to the corresponding status register
• The SPI read will clear the nFAULT report, but the SPI register will remain asserted until the condition has passed
• The nFAULT pin will report a new warning if the condition clears and then occurs again

The second error class is a Fault. Fault errors will trigger a shutdown of the gate driver with its major blocks and are reported by holding nFAULT low with the corresponding status register asserted. Fault errors are latched until the appropriate recovery sequence is performed.

• A fault error is reported by holding the nFAULT pin low and asserting the FAULT bit in register 0x1
• The error type will also be asserted in the SPI registers
• A fault error is a latched fault and must be cleared with the appropriate recovery sequence
• If a fault occurs during a warning error, the fault error will take precendence, latch nFAULT low and shutdown the gate driver
• The output MOSFETs will be placed into their high impedance state in a fault error event
• To recover from a fault type error, the condition must be removed and the CLR_FLTs bit asserted in register 0x9, bit D1 or an EN_GATE reset pulse issued
• The CLR_FLTS bit self clears to 0 after fault status reset and nFAULT pin is released

There are two exceptions to the fault and warning error classes. The first exception is the temperature flag warnings (TEMP_FLAGX). A Temperature Flag warning will not trigger any action on the nFAULT pin and the corresponding status bit will be updated in real time. See the overtemperature section for additional information. The second exception is the MCU Watchdog and VREG Undervoltage (VREG_UV) faults. These are reported on the PWRGD pin to protect the system from lock out and brownout conditions. See their corresponding sections for additional information.

Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.

7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)

DRV8305 integrates analog handshaking and digital dead time to prevent shoot-through in the external MOSFETs.

• An internal handshake through analog comparators is performed between each high-side and low-side MOSFET switching transaction (see TDRIVE: Gate Driver State Machine). The handshake monitors the voltage between the gate and source of the external MOSFET to ensure the device has reached its cutoff threshold before enabling the opposite MOSFET.
• A minimum dead time (digital) of 40 ns is always inserted after each successful handshake. This digital dead time is programmable through the DEAD_TIME SPI setting in register 0x7, bits D6-D4 and is in addition to the time taken for the analog handshake.

7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)

To protect the system and external MOSFET from damage due to high current events, V_DS overcurrent monitors are implemented in the DRV8305.

The V_DS sensing is implemented for both the high-side and low-side MOSFETs through the pins below:

• High-side MOSFET: V_DS measured between VDRAIN and SHx pins
• Low-side MOSFET: V_DS measured between SHx and SLx pins

Based on the R_DS(on) of the power MOSFETs and the maximum allowed I_DS, a voltage threshold can be calculated, which when exceeded, triggers the V_DS overcurrent protection feature. The voltage threshold level (VDS_LEVEL) is programmable through the SPI VDS_LEVEL setting in register 0xC, bits D7-D3 and may be changed during gate driver operation if needed.

The V_DS overcurrent monitors implement adjustable blanking and deglitch times to prevent false trips due to switching voltage transients. The V_DS blanking time (t_BLANK) is inserted digitally and programmable through the SPI TBLANK setting in register 0x7, bits D3-D2. The t_BLANK time is inserted after each switch ON transistion (LOW to HIGH) of the output gate drivers is commanded. During the t_BLANK time, the V_DS comparators are not being monitored in order to prevent false trips when the MOSFET first turns ON. After the t_BLANK time expires the overcurrent monitors will begin actively watching for an overcurrent event.

The V_DS deglitch time (t_VDS) is inserted digitally and programmable through the SPI TVDS setting in register 0x7, bits D1-D0. The t_VDS time is a delay inserted after the V_DS sensing comparators have tripped to when the protection logic is informed that a V_DS event has occurred. If the overcurrent event does not persist through t_VDS delay then it will be ignored by the DRV8305.

Note that the dead time and blanking time are overlapping timers as shown in Figure 13.

Figure 13. V_DS Deglitch and Blank Diagram

The DRV8305 has three possible responses to a V_DS overcurrent event. This response is set through the SPI VDS_MODE setting in register 0xC, bits D2-D0.

• V_DS Latched Shutdown Mode:

When a V_DS overcurrent event occurs, the device will pull all gate drive outputs low in order to put all six external MOSFETs into high impedance mode. The fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers.

• V_DS Report Only Mode:

In this mode, the device will take no action related to the gate drivers. When the overcurrent event is detected the fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers. The gate drivers will continue to operate normally.

• V_DS Disabled Mode:

The device ignores all the V_DS overcurrent event detections and does not report them.

7.3.8.4 Low-Side Source Monitors (SNS_OCP)

In additional to the V_DS monitors across each MOSFET, the DRV8305 directly monitors the voltage on the SLx pins with respect to ground. If high current events such phase shorts cause the SLx pin voltage to exceed 2 V, the DRV8305 will shutdown the gate driver, put the external MOSFETs into a high impedance state, and report a SNS_OCP fault error on the nFAULT pin and corresponding SPI status bit in register 0x2, bits D2-D0.

7.3.8.5 Fault and Warning Operating Modes

7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection

A multi-level temperature detection circuit is implemented in the DRV8305.

• Flag Level 1 (TEMP_FLAG1): Level 1 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D3.
• Flag Level 2 (TEMP_FLAG2): Level 2 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D2.
• Flag Level 3 (TEMP_FLAG3): Level 3 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D1.
• Flag Level 4 (TEMP_FLAG4): Level 4 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D8.
• Warning Level (OTW): Overtemperature warning only. Warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D0.
• Fault Level (OTSD): Overtemperature fault and latched shut down of the device. Fault reported on nFAULT and in SPI register 0x3, bit D8.

SPI operation is still available and register settings will be retained in the device during OTSD operation as long as PVDD is within operation range. An OTSD fault can be cleared when the device temperature has dropped below the fault level and a CLR_FLTS is issued.

7.3.9.2 Reverse Supply Protection

The DRV8305 is designed to support an external reverse supply protection scheme. The VCPH high-side charge pump is able to supply an external load up to 10 mA. This feature allows implementation of an external reverse battery protection scheme using a MOSFET and a BJT. The MOSFET gate and BJT can be driven through VCPH with a current limiting resistor. The current limiting resistor must be sized not to exceed the maximum external load on VCPH.

The VDRAIN sense pin may also be protected against reverse supply conditions by use of a current limiting resistor. The current limit resistor must be sized not to exceed the maximum current load on the VDRAIN pin. 100 Ω is recommended between VDRAIN and the drain of the external high-side MOSFET.

Figure 14. Typical Scheme for Reverse Battery Protection Using VCPH

7.3.9.3 MCU Watchdog

The DRV8305 incorporates an MCU watchdog function to ensure that the external controller that is instructing the device is active and not in an unknown state. The MCU watchdog function may be enabled by writing a 1 to the WD_EN setting in the SPI register 0x9. bit D3. The default setting for the device is with the watchdog disabled. When the watchdog is enabled, an internal timer starts to countdown to the interval set by the WD_DLY setting in the SPI register 0x9, bits D6-D5. To restart the watchdog timer, the address 0x1 (status register) must be read by the controller within the interval set by the WD_DLY setting. If the watchdog timer is allowed to expire without the address 0x1 being read, a watchdog fault will be enabled.

Response to a watchdog fault is as follows:

• A latched fault occurs on the DRV8305 and the gate drivers are put into a safe state. An appropriate recovery sequence must then be performed.
• The PWRGD pin is taken low for 56 µs and then back high in order to reset the controller or indicate the watchdog fault
• The nFAULT pin is asserted low, the WD_EN bit is cleared, and the WD_FAULT set high in register 0x3, bit D9
• It is recommended to read the status registers as part of the recovery or power-up routine in order to determine whether a WD_FAULT had previously occurred

Note that the watchdog fault results in a clearing of the WD_EN setting and it will have to be set again to resume watchdog functionality.

7.3.9.4 VREG Undervoltage (VREG_UV)

The DRV8305 has an undervoltage monitor on the VREG output regulator to ensure the external controller does not experience a brownout condition. The undervoltage monitor will signal a fault if the VREG output drops below a set threshold from its set point. The VREG output set point is configured for two different levels, 3.3 V or 5 V, depending on the DRV8305 device options (DRV83053Q and DRV83055Q). The VREG undervoltage level can be set through the SPI setting VREG_UV_LEVEL in register 0xB, bits D1-D0. The VREG undervoltage monitor can be disabled through the SPI setting DIS_VREG_PWRGD in register 0xB, bit D2.

Response to a VREG undervoltage fault is as follows:

• A latched fault occurs on the DRV8305 and the gate drivers are put into a safe state. An appropriate recovery sequence must then be performed.
• The PWRGD is taken low until the undervoltage condition is removed and for at least a minimum of 56 µs.
• The nFAULT pin is asserted low and the VREG_UV bit set high in register 0x3, bit D6.
• The fault can be cleared after the VREG undervoltage condition is removed with CLR_FLTS or an EN_GATE reset pulse

Note that the VREG undervoltage monitor is disabled on the no regulator (VREF) device option (DRV8305NQ and DRV8305NE).

7.5.1.1 SPI

The DRV8305 uses a SPI to set device configurations, operating parameters, and read out diagnostic information. The DRV8305 SPI operates in slave mode. The SPI input data (SDI) word consists of a 16 bit word with a 5 bit command and 11 bits of data. The SPI output data (SDO) word consists of 11 bits of register data with the first 5 bits (MSB) as don't cares.

A valid frame must meet following conditions:

• CPOL (clock polarity) = 0 and CPHA (clock phase) = 1
• SCLK must be low when nSCS transistions
• Full 16 SCLK cycles
• Data is always propogated on the rising edge of SCLK
• Data is always captured on the falling edge of SCLK
• MSB is shifted in and out first
• When nSCS is high, SCLK and SDI are ignored and SDO is high impedance
• nSCS should be taken high for at least 500 ns between frames
• If the data sent to SDI is less than or greater than 16 bits it is considered a frame error and the data will be ignored.

7.5.1.2 SPI Format

Figure 17. SPI Slave Mode Timing Diagram

The SPI input data (SDI) control word is 16 bits long and consists of the following format:

• 1 read or write bit W [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]

The SPI output data (SDO) word response word is 11 bits long (first 5 bits are don't cares). It contains the content of the register being accessed.

The MSB of the SDI word (W0) is the read/write bit. When W0 = 0, the input data is a write command. When W0 = 1, the input data is a read command.

For a write command: The response word is the data currently in the register being written to.

For a read command: The response word is the data currently in the register being read.

7.6.1.1 Warning and Watchdog Reset (Address = 0x1)

7.6.1.2 OV/VDS Faults (Address = 0x2)

7.6.1.3 IC Faults (Address = 0x3)

7.6.1.4 VGS Faults (Address = 0x4)

7.6.2.1 HS Gate Drive Control (Address = 0x5)

7.6.2.2 LS Gate Drive Control (Address = 0x6)

7.6.2.3 Gate Drive Control (Address = 0x7)

7.6.2.4 IC Operation (Address = 0x9)

7.6.2.5 Shunt Amplifier Control (Address = 0xA)

7.6.2.6 Voltage Regulator Control (Address = 0xB)

7.6.2.7 VDS Sense Control (Address = 0xC)