SLVSCF7B February   2014  – November 2017 DRV8308

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hall Comparators
      2. 7.3.2  FG Amplifier, Comparator, and FG Output
      3. 7.3.3  Enable, Reset, and Clock Generation
      4. 7.3.4  Commutation
        1. 7.3.4.1 120° 3-Hall Commutation
        2. 7.3.4.2 120° Single-Hall Commutation
        3. 7.3.4.3 180° Sine-Wave-Drive Commutation
      5. 7.3.5  Commutation Logic Block Diagram
      6. 7.3.6  Commutation Parameters
      7. 7.3.7  Braking
      8. 7.3.8  Output Pre-Drivers
      9. 7.3.9  Current Limit
      10. 7.3.10 Charge Pump
      11. 7.3.11 5-V Linear Regulator
      12. 7.3.12 Power Switch
      13. 7.3.13 Protection Circuits
        1. 7.3.13.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.13.2 VM Overvoltage (VMOV)
        3. 7.3.13.3 Motor Overcurrent (OCP)
        4. 7.3.13.4 Charge Pump Failure (CPFAIL)
        5. 7.3.13.5 Charge Pump Short (CPSC)
        6. 7.3.13.6 Overtemperature (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Speed Input
        1. 7.4.1.1 Clock Frequency Mode
        2. 7.4.1.2 Clock PWM and Internal Register PWM Modes
      2. 7.4.2 Auto Gain and Advance Compensation
      3. 7.4.3 External EEPROM Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Serial Data Format
      3. 7.5.3 Programming the OTP Configuration Memory
    6. 7.6 Register Map
      1. 7.6.1 Control Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Internal Speed Control Loop Constraints
      2. 8.1.2 Hall Sensor Configurations and Connections
      3. 8.1.3 FG Amplifier Configurations and Connections
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor voltage
        2. 8.2.2.2 Motor Current (Peak and RMS)
        3. 8.2.2.3 Speed Command Method
        4. 8.2.2.4 Required Flutter (Speed Jitter)
        5. 8.2.2.5 Configuration Method
        6. 8.2.2.6 Hall Element Current
        7. 8.2.2.7 Power FET Switching Time
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
      1. 8.3.1 RESET and ENABLE Considerations
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT
Power supply voltage (VM) –0.3 42 V
Charge pump and high side gate drivers (VCP, UHSG, VHSG, WHSG) –0.3 50 V
Output pin, low side gate drivers, charge pump flying cap and switched VM power supply voltage (U, V, W, ULSG, VLSG, WLSG, CP1, CP2 VSW) –0.6 40 V
Internal core voltage regulator (VINT) –0.3 2 V
Linear voltage regulator output (VREG) –0.3 5.5 V
Sense current pin (ISEN) –0.3 2 V
Digital pin voltage range (SCLK, SCS, SMODE, SDATAI, SDATAO, FGOUT, FAULTn, LOCKn, CLKIN, BRAKE, DIR, ENABLE, RESET) –0.5 5.75 V
Hall sensor input pin voltage (UHP, UHN, VHP, VHN, WHP, WHN, FGFB, FGINN/TACH, FGINP) 0 VREG V
Continuous total power dissipation See Thermal Information
Operating junction temperature range, TJ –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
(3) Power dissipation and thermal limits must be observed

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –60 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) -4000 4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) -1500 1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VM Motor power supply voltage range, ENABLE = 1, motor operating(3) 8.5 32 V
VMDIS Motor power supply voltage range, ENABLE = 0, motor not operating 4.5 35
IVREG VREG output current(1) 0 30 mA
IVSW VSW output current(1) 0 30
fHALL Hall sensor input frequency(4) 0 30 kHz
fCLKIN Frequency on CLKIN SPDMODE = 00 (Clock Frequency Mode) 0 90
SPDMODE = 01 (Clock PWM Mode) 16 50 (2)
(1) Power dissipation and thermal limits must be observed
(2) Operational with frequencies above 50 kHz, but resolution is degraded
(3) Note that at VM < 12 V, gate drive output voltage tracks VM voltage
(4) fHALL of 50 Hz to 6.7 kHz is best

6.4 Thermal Information

THERMAL METRIC(1) DRV8308 UNIT
RHA (VQFN)
40 PINS
RθJA Junction-to-ambient thermal resistance 33.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 23 °C/W
RθJB Junction-to-board thermal resistance 8.8 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 8.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VM SUPPLY
IVM VM active current ENABLE = active, VREG and VSW open 12 18 mA
ISTBY VM standby current ENABLE = inactive 120 µA
VRESET VM logic reset voltage VM falling 4.6 V
VM rising 5
VREG SUPPLY
VVREG Output voltage IOUT = 1 to 30 mA 4.75 5 5.25 V
IVREG Output current 30 mA
VSW SUPPLY
RDS(ON) VSW switch on-resistance IOUT = 1 to 30 mA 9 20 Ω
IVSW Output current 30 mA
INTERNAL CLOCK OSCILLATOR
fCLK50 Internal CLK50 clock frequency 50 MHz
LOGIC-LEVEL INPUTS AND OUTPUTS
VIL Low-level input voltage 0.8 V
VIH High-level input voltage 1.5 5.5 V
IIL Low-level input current –50 50 µA
IIH High-level input current VIN = 3.3 V, RESET, DIR, BRAKE, CLKIN, SCS, SCLK, SDATAI, SMODE 20 100 µA
VIN = 3.3 V, ENABLE 6 9
VHYS Input hysteresis voltage 0.1 0.3 0.5 V
RPD Input pulldown resistance RESET, DIR, BRAKE, CLKIN, SCS, SCLK, SDATAI, SMODE 50 100 150 kΩ
ENABLE 350 550
OPEN DRAIN OUTPUTS
VOL Low-level output voltage IOUT = 2.0 mA 0.5 V
IOH Output leakage current VOUT = 3.3 V 1 µA
FG AMPLIFIER AND COMPARATOR
VIO FG amplifier input offset voltage –7 7 mV
IIB FG amplifier input bias current –1 1 μA
VICM FG amplifier input common mode voltage range 1.5 3.5 V
AV FG amplifier open loop voltage gain 45 dB
GBW FG amplifier gain bandwidth product 500 kHz
VREF+ FG comparator positive reference voltage –20% VVREG / 2 20% V
VIT+ FG comparator positive threshold –20% VVREG / 1.8 20% V
VIT- FG comparator negative threshold –20% VVREG / 2 20% V
HALL SENSOR INPUTS
VHYS Hall amplifier hysteresis voltage 15 20 25 mV
∆VHYS Hall amplifier hysteresis difference Between U, V, W –5 5 mV
VID Hall amplifier input differential 50 mV
VCM Hall amplifier input common mode voltage range 1.5 3.5 V
IIN Input leakage current H_x+ = H_x- –10 10 μA
tHDEG Hall deglitch time 20 μs
MOSFET DRIVERS
VOUTH High-side gate drive output voltage IO = 100 μA, VM ≥ 12V VM + 10 V
VOUTL Low-side gate drive output voltage IO = 100 μA 10 V
IOUT Peak gate drive current IDRIVE = 000 10 mA
IDRIVE = 001 20
IDRIVE = 010 30
IDRIVE = 011 50
IDRIVE = 100 90
IDRIVE = 101 100
IDRIVE = 110 110
IDRIVE = 111 130
CYCLE-BY-CYCLE CURRENT LIMITER
VLIMITER Voltage limit across RISENSE for the current limiter 0.225 0.25 0.275 V
tBLANK Time that VLIMITER is ignored, from the start of the PWM cycle OCPDEG = 00 2 µs
OCPDEG = 01 3
OCPDEG = 10 3.75
OCPDEG = 11 6
PROTECTION CIRCUITS
VSENSEOCP Voltage limit across RISENSE for overcurrent protection 1.7 1.8 1.9 V
VFETOCP Voltage limit across each external FET’s drain to source for overcurrent protection OCPTH = 00 200 250 400 mV
OCPTH = 01 400 500 600
OCPTH = 10 600 750 850
OCPTH = 11 850 1000 1200
tOCP Deglitch time for VSENSEOCP or VFETOCP to trigger OCPDEG = 00 1.6 µs
OCPDEG = 01 2.3
OCPDEG = 10 3
OCPDEG = 11 5
VUVLO VM undervoltage lockout VM rising 8 V
VM falling 7.8
VOVLO VM overvoltage lockout VM rising, OVTH = 0 32 34.5 36 V
VM rising, OVTH = 1 28 29
tRETRY Fault retry time after OTS RETRY = 1 5 s
TTSD Thermal shutdown die temperature 150 160 °C
VCPFAIL VCP failure threshold (CPFAIL bit) VM + 3 V

6.6 SPI Timing Requirements

TA = 25°C, over recommended operating conditions unless otherwise noted (1)
NUMBER(2) MIN MAX UNIT
1 tCYC Clock cycle time 62 ns
2 tCLKH Clock high time 25
3 tCLKL Clock low time 25
4 tSU(SDATI) Setup time, SDATI to SCLK 5
5 tH(SDATI) Hold time, SDATI to SCLK 1
6 tSU(SCS) Setup time, SCS to SCLK 5
7 tH(SCS) Hold time, SCS to SCLK 1
8 tL(SCS) Inactive time, SCS (between writes) 100
9 tD(SDATO) Delay time, SCLK to SDATO (during read) 10
tAWAKE Wake time (ENABLE active to high-side gate drive enabled) 1 ms
tSPI Delay from power-up or RESET low until serial interface functional 10 μs
(1) SMODE = Low
(2) These numbers refer to the corresponding number in Figure 1
DRV8308 SPI_timing_req_SLVSCF7.gif Figure 1. SPI Timing Requirements

6.7 Typical Characteristics

DRV8308 VSW_vs_current_with_VM_12V_slvscf7.png
Figure 2. VSW vs Current with VM = 12V
DRV8308 VREG_vs_current_with_VM_12V_slvscf7.png
Figure 3. VREG vs Current with VM = 12V