SLVSFN2B September   2021  – February 2022 DRV8311

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Secondary Device Mode Timings
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 6x PWM Mode (DRV8311S and DRV8311H variants only)
        2. 8.3.2.2 3x PWM Mode (DRV8311S and DRV8311H variants only)
        3. 8.3.2.3 PWM Generation Mode (DRV8311S and DRV8311P Variants)
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  Propagation Delay
      9. 8.3.9  Pin Diagrams
        1. 8.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.9.3 Open Drain Pin
        4. 8.3.9.4 Push Pull Pin
        5. 8.3.9.5 Four Level Input Pin
      10. 8.3.10 Current Sense Amplifiers
        1. 8.3.10.1 Current Sense Amplifier Operation
        2. 8.3.10.2 Current Sense Amplifier Offset Correction
      11. 8.3.11 Protections
        1. 8.3.11.1 VM Supply Undervoltage Lockout (NPOR)
        2. 8.3.11.2 Under Voltage Protections (UVP)
        3. 8.3.11.3 Overcurrent Protection (OCP)
          1. 8.3.11.3.1 OCP Latched Shutdown (OCP_MODE = 010b)
          2. 8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
          3. 8.3.11.3.3 OCP Report Only (OCP_MODE = 011b)
          4. 8.3.11.3.4 OCP Disabled (OCP_MODE = 111b)
        4. 8.3.11.4 Thermal Protections
          1. 8.3.11.4.1 Thermal Warning (OTW)
          2. 8.3.11.4.2 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI and tSPI Format
  9. 9 DRV8311 Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Three-Phase Brushless-DC Motor Control
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Motor Voltage
        2. 10.2.1.2 Driver Propagation Delay and Dead Time
        3. 10.2.1.3 Delay Compensation
        4. 10.2.1.4 Current Sensing and Output Filtering
        5. 10.2.1.5 Application Curves
    3. 10.3 Three Phase Brushless-DC tSPI Motor Control
      1. 10.3.1 Detailed Design Procedure
    4. 10.4 Alternate Applications
  11. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Power Dissipation and Junction Temperature Estimation
  13. 13Device and Documentation Support
    1. 13.1 Support Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

Figure 6-1 DRV8311S 24-Pin WQFN With Exposed Thermal Pad Top View
Figure 6-2 DRV8311H 24-Pin WQFN With Exposed Thermal Pad Top View
Figure 6-3 DRV8311P 24-Pin WQFN With Exposed Thermal Pad Top View
Table 6-1 Pin Functions
PIN 24-pin Package TYPE(1) DESCRIPTION
NAME DRV8311H DRV8311P DRV8311S
AD0 — 15 — I Only on tSPI device DRV8311P. Address selection for tSPI.
AD1 — 14 — I Only on tSPI device DRV8311P. Address selection for tSPI.
AGND 16 16 16 PWR Device analog ground. Connect to system ground.
AVDD 17 17 17 PWR 3.3V regulator output. Connect a X5R or X7R, 0.7-µF to 7-µF, 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 100 mA externally.
CP 6 6 6 PWR Charge pump output. Connect a X5R or X7R, 0.1-µF, 16-V ceramic capacitor between the VCP and VM pins.
CSAREF 2 2 2 PWR Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.
GAIN 21 — — I Only on Hardware devices (DRV8311H). Current sense amplifier gain setting. The pin is a 4 level input pin configured by an external resistor between GAIN and AVDD or AGND.
INHA 15 — 15 I High-side driver control input for OUTA. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INHB 14 — 14 I High-side driver control input for OUTB. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INHC 13 — 13 I High-side driver control input for OUTC. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode.
INLA 18 — 18 I Low-side driver control input for OUTA. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
INLB 19 — 19 I Low-side driver control input for OUTB. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
INLC 20 — 20 I Low-side driver control input for OUTC. This pin controls the state of the low-side MOSFET in 6x PWM Mode.
MODE 23 — — I Only on Hardware devices (DRV8311H). PWM mode setting. This pin is a 4 level input pin configured by an external resistor between MODE and AVDD or AGND.
nFAULT 1 1 1 O Fault indication pin. Pulled logic-low with fault condition; open-drain output requires an external pullup to AVDD.
nSCS — 20 24 I Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial chip select. A logic low on this pin enables serial interface communication (SPI devices).
nSLEEP 24 24 — I Only on DRV8311H and DRV8311P devices. When this pin is logic low the device goes to a low-power sleep mode. A 15 to 50-µs low pulse on nSLEEP pin can be used to reset fault conditions without entering sleep mode.
OUTA 10 10 10 O Half bridge output A. Connect to motor winding.
OUTB 11 11 11 O Half bridge output B. Connect to motor winding.
OUTC 12 12 12 O Half bridge output C. Connect to motor winding.
PGND 9 9 9 PWR Device power ground. Connect to system ground.
PWM_SYNC — 19 — I Only on tSPI device DRV8311P. Connect to the MCU signal to synchronize the internally-generated PWM signals from DRV8311 to the MCU in PWM generation mode.
SCLK — 23 23 I Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial clock input. Serial data is shifted out on the rising edge and captured on the falling edge of SCLK (SPI devices).
SDI — 22 22 I Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial data input. Data is captured on the falling edge of the SCLK pin (SPI devices).
SDO — 21 21 O Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial data output. Data is shifted out on the rising edge of the SCLK pin.
SLEW 22 — — I Only on DRV8311H device. OUTx voltage slew rate control setting. This pin is a 4 level input pin set by an external resistor between SLEW pin and AVDD or AGND.
SOA 5 5 5 O Current sense amplifier output for OUTA.
SOB 4 4 4 O Current sense amplifier output for OUTB.
SOC 3 3 3 O Current sense amplifier output for OUTC.
VM 8 8 8 PWR Power supply for the motor. Connect to motor supply voltage. Connect a X5R or X7R, 0.1-uF VM-rated ceramic bypass capacitor as well as a >=10-uF, VM-rated bulk capacitor between VM and PGND. Additionally, connect a X5R or X7R, 0.1-uF, 16-V ceramic capacitor between the VM and CP pins.
VIN_AVDD 7 7 7 PWR Supply input for AVDD. Bypass to AGND with a X5R or X7R, 0.1-uF, VIN_AVDD-rated ceramic capacitor as well as a >=10-uF, VIN_AVDD-rated rated bulk capacitor between VIN_AVDD and PGND.
Thermal pad PWR Must be connected to PGND.
NC — 13,18 — — No connect. Leave the pin floating.
(1) I = input, O = output, PWR = power, NC = no connect