SLVSFN2B September   2021  – February 2022 DRV8311

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Secondary Device Mode Timings
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 6x PWM Mode (DRV8311S and DRV8311H variants only)
        2. 8.3.2.2 3x PWM Mode (DRV8311S and DRV8311H variants only)
        3. 8.3.2.3 PWM Generation Mode (DRV8311S and DRV8311P Variants)
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  Propagation Delay
      9. 8.3.9  Pin Diagrams
        1. 8.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.9.3 Open Drain Pin
        4. 8.3.9.4 Push Pull Pin
        5. 8.3.9.5 Four Level Input Pin
      10. 8.3.10 Current Sense Amplifiers
        1. 8.3.10.1 Current Sense Amplifier Operation
        2. 8.3.10.2 Current Sense Amplifier Offset Correction
      11. 8.3.11 Protections
        1. 8.3.11.1 VM Supply Undervoltage Lockout (NPOR)
        2. 8.3.11.2 Under Voltage Protections (UVP)
        3. 8.3.11.3 Overcurrent Protection (OCP)
          1. 8.3.11.3.1 OCP Latched Shutdown (OCP_MODE = 010b)
          2. 8.3.11.3.2 OCP Automatic Retry (OCP_MODE = 000b or 001b)
          3. 8.3.11.3.3 OCP Report Only (OCP_MODE = 011b)
          4. 8.3.11.3.4 OCP Disabled (OCP_MODE = 111b)
        4. 8.3.11.4 Thermal Protections
          1. 8.3.11.4.1 Thermal Warning (OTW)
          2. 8.3.11.4.2 Thermal Shutdown (OTSD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI and tSPI Format
  9. 9 DRV8311 Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Three-Phase Brushless-DC Motor Control
        1. 10.2.1.1 Detailed Design Procedure
          1. 10.2.1.1.1 Motor Voltage
        2. 10.2.1.2 Driver Propagation Delay and Dead Time
        3. 10.2.1.3 Delay Compensation
        4. 10.2.1.4 Current Sensing and Output Filtering
        5. 10.2.1.5 Application Curves
    3. 10.3 Three Phase Brushless-DC tSPI Motor Control
      1. 10.3.1 Detailed Design Procedure
    4. 10.4 Alternate Applications
  11. 11Power Supply Recommendations
    1. 11.1 Bulk Capacitance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Power Dissipation and Junction Temperature Estimation
  13. 13Device and Documentation Support
    1. 13.1 Support Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

at TJ = –40°C to +150°C, VVM = 3 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVMQ VM sleep mode current VVM = 12 V, nSLEEP = 0, TA = 25 °C 1.5 3 µA
nSLEEP = 0, TA = 125 °C 9 µA
IVMS VM standby mode current VVM = 12 V, nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF', TA = 25 °C 7 12 mA
nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF' 8 12 mA
IVM VM operating mode current VVM = 12 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C 10 13 mA
VVM = 12 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C 12 14 mA
nSLEEP =1, fPWM = 25 kHz 10 15 mA
nSLEEP =1, fPWM = 200 kHz 12 15 mA
VAVDD Analog regulator voltage VVM > 4V, VVIN_AVDD > 4.5V, 0 mA ≤ IAVDD ≤ 100 mA 3.15 3.3 3.45 V
VAVDD VVM > 3.5V, 3.5V ≤VVIN_AVDD ≤ 4.5V, 0 mA ≤ IAVDD ≤ 35 mA 3 3.3 3.6 V
VAVDD 2.5V ≤VVIN_AVDD ≤ 3.5V, 0 mA ≤ IAVDD ≤ 10 mA 2.2 VIN_AVDD-0.3 3.4 V
VAVDD VVM < 4V, VVIN_AVDD > 4.5V, 0 mA ≤ IAVDD ≤ 40 mA 3 3.3 3.6 V
VAVDD VVM < 3.5V, 3.5V ≤VVIN_AVDD ≤ 4.5V, 0 mA ≤ IAVDD ≤ 20 mA 3 3.3 3.6 V
IAVDD_LIM External analog regulator current limit  148 200 250 mA
IAVDD External analog regulator load VVM > 4V, VVIN_AVDD > 4.5V 100 mA
VVM < 4V, VVIN_AVDD > 4.5V 40 mA
VVM > 3.5V, 3.6V ≤VVIN_AVDD ≤ 4.5V 35 mA
VVM < 3.5V, 3.6V ≤VVIN_AVDD ≤ 4.5V 20 mA
2.5V ≤VVIN_AVDD ≤ 3.6V 10 mA
CAVDD Capacitance on AVDD pin IAVDD ≤ 25 mA;  0.7 1 7 µF
IAVDD ≥ 25 mA;  3.3 4.7 7 µF
RAVDD AVDD Output Voltage Regulation VVIN_AVDD > 4.5V; IAVDD ≤ 20 mA;  -3 3 %
VVIN_AVDD > 4.5V; 20 mA ≤ IAVDD ≤ 40 mA;  -2 2 %
VVIN_AVDD > 4.5V;  IAVDD ≥ 40 mA;  -3 3 %
VVCP Charge pump regulator voltage VCP with respect to VM 3 5 5.6 V
tWAKE Wakeup time VVM > VUVLO, nSLEEP = 1 to Output ready 1 3 ms
tWAKE_CSA Wakeup time for CSA VCSAREF > VCSAREF_UV to SOx ready, when nSLEEP = 1 30 50 µs
tSLEEP Turn-off time nSLEEP = 0 to driver tri-stated 100 200 µs
tRST Reset Pulse time nSLEEP = 0 period to reset faults 10 65 µs
LOGIC-LEVEL INPUTS (INHx, INLx, nSLEEP, SCLK, SDI)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.65 5.5 V
VHYS Input logic hysteresis 100 300 660 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –1 1 µA
IIH Input logic high current nSLEEP, VPIN (Pin Voltage) = 5 V 30 µA
Other pins, VPIN (Pin Voltage) = 5 V 50 µA
RPD Input pulldown resistance nSLEEP 230 300 kΩ
Other pins 160 200 kΩ
CID Input capacitance 30 pF
LOGIC-LEVEL INPUTS (nSCS)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 200 500 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V 90 µA
IIH Input logic high current VPIN (Pin Voltage) = 5 V 70 µA
RPU Input pullup resistance 48 90 kΩ
CID Input capacitance 30 pF
FOUR-LEVEL INPUTS (GAIN, MODE, SLEW)
VL1 Input mode 1 voltage Tied to AGND 0 0.21*AVDD V
VL2 Input mode 2 voltage 47 kΩ +/- 5% tied to GND 0.25*AVDD 0.5*AVDD 0.55*AVDD V
VL3 Input mode 3 voltage Hi-Z 0.606*AVDD 0.757*AVDD 0.909*AVDD V
VL4 Input mode 4 voltage Tied to AVDD 0.94*AVDD AVDD V
RPU Input pullup resistance To AVDD 48 70 kΩ
RPD Input pulldown resistance To AGND 160 200 kΩ
OPEN-DRAIN OUTPUTS (nFAULT)
VOL Output logic low voltage IOD = -5 mA 0.4 V
IOH Output logic high current VOD = 5 V –1 1 µA
COD Output capacitance 30 pF
PUSH-PULL OUTPUTS (SDO)
VOL Output logic low voltage IOP = -5 mA, 2.2V ≤ VAVDD ≤ 3V 0 0.55 V
IOP = -5 mA, 3V ≤ VAVDD ≤ 3.6V 0 0.5 V
VOH Output logic high voltage IOP = 5 mA, 2.2V ≤ VAVDD ≤ 3V VAVDD - 0.86 3 V
IOP = 5 mA, 3V ≤ VAVDD ≤ 3.6V VAVDD - 0.5 3.6 V
IOL Output logic low current VOP = 0 V –1 1 µA
IOH Output logic high current VOP = 5 V –1 1 µA
COD Output capacitance 30 pF
DRIVER OUTPUTS
RDS(ON) Total MOSFET on resistance (High-side + Low-side) 6V ≥ VVM ≥ 3 V, IOUT = 1 A, TJ = 25°C 300 350 mΩ
6V ≥ VVM ≥ 3 V, IOUT = 1 A, TJ = 150°C 450 500 mΩ
VVM ≥ 6 V, IOUT = 1 A, TJ = 25°C 210 250 mΩ
VVM ≥ 6 V, IOUT = 1 A, TJ = 150°C 330 375 mΩ
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 % of VM) VVM = 12V; SLEW = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) 18 35 55 V/us
SR VVM = 12V; SLEW = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) 35 75 100 V/us
SR VVM = 12V; SLEW = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) 90 180 225 V/us
SR VVM = 12V; SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) 140 230 355 Vus
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 % of VM)
 		 VVM = 12V; SLEW = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) 20 35 50 V/us
VVM = 12V; SLEW = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) 35 75 100 V/us
VVM = 12V; SLEW = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) 80 180 225 V/us
VVM = 12V; SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) 125 270 350 V/us
tDEAD Output dead time (high to low / low to high) VVM = 12V, SLEW = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant), DEADTIME = 000b, Handshake only  500 1200 ns
VVM = 12V, SLEW = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant), DEADTIME = 000b, Handshake only   450 760 ns
VVM = 12V, SLEW = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant), DEADTIME = 000b, Handshake only   425 720 ns
VVM = 12V, SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant), DEADTIME = 000b; Handshake only   425 710 ns
VVM = 12 V, DEADTIME = 001b 200 540 ns
VVM = 12 V, DEADTIME = 010b 400 550 ns
VVM = 12 V, DEADTIME = 011b 600 760 ns
VVM = 12 V, DEADTIME = 100b 800 900 ns
VVM = 12 V, DEADTIME = 101b 1000 1100 ns
VVM = 12 V, DEADTIME = 110b 1200 1300 ns
VVM = 12 V, DEADTIME = 111b 1400 1500 ns
tPD Propagation delay (high-side / low-side ON/OFF) INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) 1000 1500 ns
INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) 650 1100 ns
INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) 550 950 ns
INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) 500 910 ns
tMIN_PULSE Minimum output pulse width SLEW = 11b 500 ns
CURRENT SENSE AMPLIFIER
GCSA Current sense gain (SPI Device) CSA_GAIN = 00 (SPI Variant) or GAIN pin tied to AGND (HW Variant) 0.25 V/A
CSA_GAIN = 01 (SPI Variant) or GAIN pin to 47 kΩ +/- 5% tied to GND (HW Variant) 0.5 V/A
CSA_GAIN = 10 (SPI Variant) or GAIN pin to Hi-Z (HW Variant) 1 V/A
CSA_GAIN = 11 (SPI Variant) or GAIN pin tied to AVDD (HW Variant) 2 V/A
GCSA_ERR Current sense gain error TJ = 25°C, IPHASE < 2.5 A –4 4 %
TJ = 25°C, IPHASE > 2.5 A –5 5 %
IPHASE < 2.5 A –5.5 5.5 %
IPHASE > 2.5 A –7 7 %
IMATCH Current sense gain error matching between phases A, B and C TJ = 25°C –5 5 %
–5 5 %
FSPOS Full scale positive current measurement 5 A
FSNEG Full scale negative current measurement –5 A
VLINEAR SOX output voltage linear range 0.25 VCSAREF – 0.25 V
IOFFSET_RT Current sense offset low side current in (Room Temperature) TJ = 25°C, Phase current = 0 A, GCSA = 0.25 V/A –50 50 mA
TJ = 25°C, Phase current = 0 A, GCSA = 0.5 V/A –50 50 mA
TJ = 25°C, Phase current = 0 A, GCSA = 1 V/A –30 30 mA
TJ = 25°C, Phase current = 0 A, GCSA = 2 V/A –30 30 mA
IOFFSET Current sense offset referred to low side current in Phase current = 0 A, GCSA = 0.25 V/A –70 70 mA
Phase current = 0 A, GCSA = 0.5 V/A –50 50 mA
Phase current = 0 A, GCSA = 1 V/A –50 50 mA
Phase current = 0 A, GCSA = 2 V/A –50 50 mA
tSET Settling time to ±1%, 30 pF on SOx pin Step on SOx = 1.2 V, GCSA = 0.25 V/A 1 μs
Step on SOx = 1.2 V, GCSA = 0.5 V/A 1 μs
Step on SOx = 1.2 V, GCSA = 1 V/A 1 μs
Step on SOx = 1.2 V, GCSA = 2 V/A 1 μs
VDRIFT Drift offset Phase current = 0 A –150 150 µA/℃
ICSAREF CSAREF input current CSAREF = 3.0 V 1.7 3 mA
PROTECTION CIRCUITS
VUVLO Supply undervoltage lockout (UVLO) VM rising 2.6 2.7 2.8 V
VM falling 2.5 2.6 2.7 V
VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold 60 125 210 mV
tUVLO Supply undervoltage deglitch time 5 7.5 13 µs
VVINAVDD_UV AVDD supply input undervoltage lockout (VINAVDD_UV) VIN_AVDD rising 2.6 2.7 2.8 V
VIN_AVDD falling 2.5 2.6 2.7 V
VVINAVDD_UV_HYS AVDD supply input undervoltage lockout hysteresis Rising to falling threshold 100 125 150 mV
tVINAVDD_UV AVDD supply input undervoltage deglitch time 2.5 4 5 µs
VCPUV Charge pump undervoltage lockout (voltage with respect to VM) VCP rising 2 2.3 2.5 V
VCP falling 2 2.2 2.4 V
VCPUV_HYS Charge pump undervoltage lockout hysteresis Rising to falling threshold 65 100 125 mV
tCPUV Charge pump undervoltage lockout deglitch time 0.2 0.5 µs
VCSAREF_UV CSA reference undervoltage lockout VCSAREF rising 1.68 1.8 1.95 V
VCSAREF_UV CSA reference undervoltage lockout VCSAREF falling 1.6 1.7 1.85 V
VCSAREF_UV_HYS CSA reference undervoltage lockout hysteresis Rising to falling threshold 70 90 110 mV
VAVDD_UV Analog regulator undervoltage lockout VAVDD rising 1.8 2 2.2 V
VAVDD falling 1.7 1.8 1.95 V
IOCP Overcurrent protection trip point OCP_LVL = 0 (SPI Variant) or MODE pin tied to AGND or MODE pin to Hi-Z (HW Variant) 5.8 9 11.5 A
OCP_LVL = 1 (SPI Variant) or MODE pin tied to AVDD or MODE pin 47 kΩ +/- 5% tied to AGND  (HW Variant) 3.4 5 7.5 A
tBLANK Overcurrent protection blanking time (SPI Variant) OCP_TBLANK = 00b 0.2 µs
OCP_TBLANK = 01b 0.5 µs
OCP_TBLANK = 10b 0.8 µs
OCP_TBLANK = 10b 1 µs
tBLANK Overcurrent protection blanking time (HW Variant) 0.2 µs
tOCP_DEG Overcurrent protection deglitch time (SPI Variant) OCP_DEG = 00b 0.2 µs
OCP_DEG = 01b 0.5 µs
OCP_DEG = 10b 0.8 µs
OCP_DEG = 11b 1 µs
tOCP_DEG Overcurrent protection deglitch time (HW Variant) 1 µs
tRETRY Overcurrent protection retry time (SPI Variant) FAST_RETRY = 00b 0.24 0.5 0.65 ms
FAST_RETRY = 01b 0.7 1 1.2 ms
FAST_RETRY = 10b 1.6 2 2.2 ms
FAST_RETRY = 11b 4.4 5 5.3 ms
SLOW_RETRY = 00b 390 500 525 ms
SLOW_RETRY = 01b 840 1000 1050 ms
SLOW_RETRY = 10b 1700 2000 2200 ms
SLOW_RETRY = 11b 4400 5000 5400 ms
tRETRY Overcurrent protection retry time (HW Variant) 5 ms
TOTW Thermal warning temperature Die temperature (TJ) Rising 170 178 185 °C
TOTW_HYS Thermal warning hysteresis Die temperature (TJ) 25 30 °C
TTSD Thermal shutdown temperature Die temperature (TJ) Rising 180 190 200 °C
TTSD_HYS Thermal shutdown hysteresis Die temperature (TJ) 25 30 °C
TTSD Thermal shutdown temperature (LDO) Die temperature (TJ) Rising 180 190 200 °C
TTSD_HYS Thermal shutdown hysteresis (LDO) Die temperature (TJ) 25 30 °C
PWM OUTPUT ACCURACY (tSPI)
RPWM Output PWM Resolution PWM FREQUENCY = 20 kHz 10 bits
APWM Output PWM Accuracy  VVM < 4.5V, PWM_SYNC and Clock Tuning Disabled -7.5 7.5 %
VVM > 4.5V, PWM_SYNC and Clock Tuning Disabled -4 4 %
PWM_SYNC Enabled and Clock Tuning Disabled -1 1 %
PWM_SYNC Disabled and SPISYNC_ACRCY = 11b -2 2 %
PWM_SYNC Disabled and SPISYNC_ACRCY = 10b -1 1 %
PWM_SYNC Disabled and SPISYNC_ACRCY = 01b -1 1 %
PWM_SYNC Disabled and SPISYNC_ACRCY = 00b -1 1 %