SLVSGK9 January 2022 DRV8316-Q1
PRODUCTION DATA
Figure 8-22 shows the input structure for the logic level pins, DRVOFF, INHx, INLx, nSLEEP, SCLK and SDI. The input can be with a voltage or external resistor. It is recommended to put these pins low in device sleep mode to reduce leakage current through internal pull-down resistors.