DRV8317 provides three integrated MOSFET half-bridges for driving three-phase brushless DC (BLDC) motors with 5-V, 9-V, 12-V, or 18-V DC rails or 2s to 4s batteries. The device provides integrated three-phase current sensing which eliminates the need for external sense resistors. DRV8317 has an integrated LDO that provides a regulated 3.3-V rail capable of delivering up to 80mA for external loads like MCU, logic circuits, hall sensors etc.,
DRV8317 provides a configurable 6x or 3x PWM control scheme which can be used to implement sensored or sensorless field-oriented control (FOC), sinusoidal control, or trapezoidal control using an external microcontroller. DRV8317 is capable of driving a PWM frequency of up to 200 kHz. DRV8317 is highly configurable either through SPI (DRV8317S) or pins (DRV8317H) - PWM mode, slew rate, current sense gain are some of the configurable features.
A number of protection features including supply under voltage lockout (UVLO), over voltage protection (OVP), charge pump under voltage (CPUV), over current protection (OCP), over temperature warning (OTW) and over temperature shutdown (OTS) are integrated into DRV8317 to protect the device, motor, and system against fault events. Fault conditions are indicated by the nFAULT pin.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8317S(2) | WQFN (36) | 5.00 mm × 4.00 mm |
DRV8317H | WQFN (36) | 5.00 mm × 4.00 mm |
DATE | REVISION | NOTES |
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April 2022 | * | Initial release |
DEVICE | PACKAGES | INTERFACE |
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DRV8317S | 36-pin WQFN (5-mm x 4-mm) | SPI |
DRV8317H | Hardware (Pin) |
Parameters | DRV8317S | DRV8317H |
---|---|---|
PWM control mode | PWM_MODE (4 settings) | MODE pin (2 settings) |
Slew rate | SLEW_RATE (4 settings) | SLEW pin (4 settings) |
Current sense amplifier gain | CSA_GAIN (4 settings) | GAIN pin (4 settings) |
OCP blanking time | OCP_TBLANK (4 settings) | Fixed to 0.7-µs |
OCP deglitch time | OCP_DEG (4 settings) | Fixed to 0.6-µs |
OCP mode | OCP_MODE (4 settings), Configurable retry time | 5-ms automatic retry |
Dead time | Fixed based on SLEW_RATE setting | Fixed based on SLEW pin setting |
Propagation delay | Fixed based on SLEW_RATE setting | Fixed based on SLEW pin setting |
Driver delay compensation | DLYCMP_EN (2 settings) | Disabled |
Spread Spectrum Clock for internal oscillator | SSC_DIS (2 settings) | Enabled |
VM under voltage lockout | VM under voltage protection always enabled. VM under voltage protection mode set by UVP_MODE (2 settings); configurable retry time using SLOW_TRETRY and FAST_TRETRY. | VM under voltage protection always enabled. Auto-retry mode for VM under voltage with 5-ms retry time. |
VIN_AVDD, AVDD under voltage lockout | VIN_AVDD and AVDD under voltage protection always enabled. Device resets on VIN_AVDD or AVDD under voltage. | VIN_AVDD and AVDD under voltage protection always enabled. Device resets on VIN_AVDD or AVDD under voltage. |
CP under voltage lockout | CP under voltage protection always enabled. CP under voltage protection mode set by UVP_MODE (2 settings); configurable retry time using SLOW_TRETRY and FAST_TRETRY. | CP under voltage protection always enabled. Auto-retry mode for CP under voltage with 5-ms retry time. |
VM over voltage | OVP_MODE (2 settings); configurable retry time using SLOW_TRETRY and FAST_TRETRY | 5-ms automatic retry |
SPI fault | SPIFLT_MODE (2 settings) | N/A |
FET over temperature warning (OTW_FET) | Enable/disable using OTW_FET_EN. If enabled, over temperature warning is reported on nFAULT pin and OTW_FET bit in OT_STS register. | Disabled |
FET over temperature shutdown (OTS_FET) | OTF_MODE (2 settings); configurable retry time using SLOW_TRETRY and FAST_TRETRY | 5-ms automatic retry |
PIN | 36-pin package | TYPE(1) | DESCRIPTION | |
---|---|---|---|---|
NAME | DRV8317S | DRV8317H | ||
AGND | 21 | 21 | GND | Device analog ground. Connect to a separate ground plane.2 |
AVDD | 22 | 22 | PWR O | 3.3V regulator output. Connect a X5R or X7R, 2.2-µF (no load) or 4.7-µF (up to 80mA load), 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 80 mA for external loads. |
CP | 6 | 6 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and VM pins. |
CPH | 5 | 5 | PWR | Charge pump switching node. Connect a X5R or X7R, 100-nF, (2xVM)- rated ceramic capacitor between the CPH and CPL pins. |
CPL | 4 | 4 | PWR | |
CSAREF | 33 | 33 | PWR I | Current sense amplifier power supply input/reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins. |
GAIN | — | 29 | I | Available only in hardware variant (DRV8317H). The pin is a 4-level input pin for current sense amplifier gain setting. |
INHA | 23 | 23 | I | High-side driver control input for OUTA. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode. |
INHB | 25 | 25 | I | High-side driver control input for OUTB. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode. |
INHC | 27 | 27 | I | High-side driver control input for OUTC. This pin controls the state of the high-side MOSFET in 6x/3x PWM Mode. |
INLA | 24 | 24 | I | Low-side driver control input for OUTA. This pin controls the state of the low-side MOSFET in 6x PWM Mode. |
INLB | 26 | 26 | I | Low-side driver control input for OUTB. This pin controls the state of the low-side MOSFET in 6x PWM Mode. |
INLC | 28 | 28 | I | Low-side driver control input for OUTC. This pin controls the state of the low-side MOSFET in 6x PWM Mode. |
MODE | — | 31 | I | Available only in hardware variant (DRV8317H). This is a 4-level input pin for PWM mode setting. |
NC | 3 | 3, 32 | — | No connect. Leave the pin floating. |
nFAULT | 2 | 2 | O | Fault indication pin. Pulled low during fault condition. Open-drain output; requires an external pull-up resistor to AVDD. |
nSCS | 32 | — | I | Available only in SPI variant (DRV8317S). Serial chip select. A logic low on this pin enables serial interface communication. |
nSLEEP | 1 | 1 | I | When this pin is logic low the device goes to a low-power sleep mode. A 15 to 50-µs low pulse on nSLEEP pin can be used to reset fault conditions without entering sleep mode. |
OUTA | 11, 12 | 11, 12 | O | Half-bridge output A. Connect to motor winding. |
OUTB | 14, 15 | 14, 15 | O | Half-bridge output B. Connect to motor winding. |
OUTC | 17, 18 | 17, 18 | O | Half-bridge output C. Connect to motor winding. |
PGND | 10, 13, 16, 19 | 10, 13, 16, 19 | PWR | Device power ground. Connect to a separate ground plane.2 |
SCLK | 31 | — | I | Available only in SPI variant (DRV8317S). Serial clock input. Serial data is shifted out on the rising edge and captured on the falling edge of SCLK. |
SDI | 30 | — | I | Available only in SPI variant (DRV8317S). Serial data input. Data (input) is captured on the falling edge of the SCLK pin (SPI devices). |
SDO | 29 | — | O | Available only in SPI variant (DRV8317S). Serial data output. Data (output) is shifted out on the rising edge of the SCLK pin. |
SLEW | — | 30 | I | Available only in hardware variant (DRV8317H). This pin is a 4-level input pin for OUTx voltage slew rate setting. |
SOA | 36 | 36 | O | Current sense amplifier output for OUTA. |
SOB | 35 | 35 | O | Current sense amplifier output for OUTB. |
SOC | 34 | 34 | O | Current sense amplifier output for OUTC. |
VIN_AVDD | 7 | 7 | PWR | Input supply for AVDD LDO |
VM | 8, 9, 20 | 8, 9, 20 | PWR | Device and motor power supply. Connect to motor supply voltage; bypass to PGND with a 0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device |
Thermal pad | PWR | Must be connected to AGND. |