SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
Table 8-9 lists the memory-mapped registers for the DRV8317 registers. All register offset addresses not listed in Table 8-9 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DEV_STS | Device Status Register | #DRV8317_DRV8317_DRV8317_DEV_STS |
2h | DEV_RSTS | Device Raw Status Register | #DRV8317_DRV8317_DRV8317_DEV_RSTS |
4h | OT_STS | Over Temperature Status Register | #DRV8317_DRV8317_DRV8317_OT_STS |
5h | SUP_STS | Supply Status Register | #DRV8317_DRV8317_DRV8317_SUP_STS |
6h | DRV_STS | Driver Status Register | #DRV8317_DRV8317_DRV8317_DRV_STS |
7h | SYSIF_STS | System Interface Status Register | #DRV8317_DRV8317_DRV8317_SYSIF_STS |
10h | FLT_MODE | Fault Mode Register | #DRV8317_DRV8317_DRV8317_FLT_MODE |
12h | SYSF_CTRL | System Fault Control Register | #DRV8317_DRV8317_DRV8317_SYSF_CTRL |
13h | DRVF_TCTRL | Driver Fault Control Register | #DRV8317_DRV8317_DRV8317_DRVF_TCTRL |
16h | FLT_TCTRL | Fault Timing Control Register | #DRV8317_DRV8317_DRV8317_FLT_TCTRL |
17h | FLT_CLR | Fault Clear Register | #DRV8317_DRV8317_DRV8317_FLT_CLR |
18h | VMUV_WARN_THR | VM Under Voltage Warn Threshold Register | #DRV8317_DRV8317_DRV8317_VMUV_WARN_THR |
20h | PWM_CTRL | PWM Control Register | #DRV8317_DRV8317_DRV8317_PWM_CTRL |
22h | DRV_CTRL | Predriver control Register | #DRV8317_DRV8317_DRV8317_DRV_CTRL |
23h | CSA_CTRL | CSA Control Register | #DRV8317_DRV8317_DRV8317_CSA_CTRL |
3Fh | SYS_CTRL | System Control Register | #DRV8317_DRV8317_DRV8317_SYS_CTRL |
Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DEV_STS is shown in Figure 8-28 and described in Table 8-11.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | DNRDY_STS | SYSFLT | ||||
R-0h | R-0-0h | R-0-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET | SPIFLT | OCP | UVW | OVP | UVP | OTF | FAULT |
R-1h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-10 | RESERVED | R-0 | 0h | Reserved |
9 | DNRDY_STS | R-0 | 1h | Device not ready status
0h = Device is ready to spin motor 1h = Device is not ready |
8 | SYSFLT | R | 0h | OTP read fault occurred. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No OTP read fault is detected 1h = OTP read fault detected |
7 | RESET | R | 1h | Device power on status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = Cleared by writing 1b to FLT_CLR bit after power-up 1h = Device has undergone power on reset |
6 | SPIFLT | R | 0h | SPI fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No SPI fault is detected 1h = SPI fault is detected |
5 | OCP | R | 0h | Driver over current Status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No over current condition is detected 1h = Over current condition is detected |
4 | UVW | R | 0h | VM under voltage warning fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No VM under voltage warn condition is detected 1h = VM under voltage warn condition is detected |
3 | OVP | R | 0h | Over voltage status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No over voltage condition is detected 1h = Over voltage condition is detected |
2 | UVP | R | 0h | Supply under voltage status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No under voltage condition is detected on VM or CP 1h = Under voltage condition is detected on VM or CP |
1 | OTF | R | 0h | Over temperature fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No over temperature warning / shutdown is detected 1h = Over temperature warning / shutdown is detected |
0 | FAULT | R | 0h | Device fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No fault condition is detected 1h = Fault condition is detected |
DEV_RSTS is shown in Figure 8-29 and described in Table 8-12.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DNRDY_RSTS | SYSF_RSTS | |||||
R-0-0h | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SPIF_RSTS | OCP_RSTS | VMUV_WRSTS | OVP_RSTS | UVP_RSTS | OTF_RSTS | RESERVED |
R-0-0h | R-0h | R-0h | R-0-0h | R-0-0h | R-0h | R-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-10 | RESERVED | R-0 | 0h | Reserved |
9 | DNRDY_RSTS | R | 0h | Device not ready indicator
0h = Device not ready to drive PWMs 1h = Device ready to drive PWMs |
8 | SYSF_RSTS | R | 0h | OTP parity error during load, raw status. Cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No parity error during OTP load 1h = Parity error occurred during OTP load |
7 | RESERVED | R-0 | 0h | Reserved |
6 | SPIF_RSTS | R | 0h | SPI fault raw status. Cleared by write to FLT_CLR or reset pulse on nSLEEP
0h = No SPI fault is detected 1h = SPI fault is detected |
5 | OCP_RSTS | R | 0h | Driver OCP raw status. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current condition is detected 1h = Over current condition is detected |
4 | VMUV_WRSTS | R-0 | 0h | VM under voltage warning fault raw status. Auto cleared if retry is enabled in VMUV_WARN_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM under voltage warn condition is detected (VM > VMUV_WARN_RISE threshold) 1h = VM under voltage warn condition is detected (VM < VMUV_WARN_FALL threshold) |
3 | OVP_RSTS | R-0 | 0h | Over voltage protection fault raw status. Auto cleared if retry is enabled in OVP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over voltage condition on VM is detected 1h = VM over voltage condition is detected |
2 | UVP_RSTS | R | 0h | Under voltage protection fault raw status. Auto cleared if retry is enabled in UVP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No under voltage condition is detected on VM or CP 1h = Under voltage condition is detected on VM or CP |
1 | OTF_RSTS | R | 0h | Over temperature fault raw status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over temperature warning/shutdown is detected 1h = Over temperature warning/shutdown is detected |
0 | RESERVED | R-0 | 0h | Reserved |
OT_STS is shown in Figure 8-30 and described in Table 8-13.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | OTW_FET | OTS_FET | ||||
R-0-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | OTW_FET | R | 0h | FET over temperature warning fault status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No FET over temperature warning is detected 1h = FET over temperature warning is detected |
0 | OTS_FET | R | 0h | FET over temperature shutdown fault status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No FET over temperature shutdown is detected 1h = FET over temperature shutdown is detected |
SUP_STS is shown in Figure 8-31 and described in Table 8-14.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VMUV_WARN | VM_OV | RESERVED | CP_UV | RESERVED | RESERVED | VM_UV | RESERVED |
R-0-0h | R-0-0h | R-0-0h | R-0h | R-0-0h | R-0h | R-0-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-8 | RESERVED | R-0 | 0h | Reserved |
7 | VMUV_WARN | R-0 | 0h | VM under voltage warning fault status. This bit is not auto cleared even when retry is enabled in VMUV_WARN_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM under voltage warning is detected 1h = VM under voltage warning is detected |
6 | VM_OV | R-0 | 0h | VM over voltage fault status. This bit is not auto cleared even when retry is enabled in OVP_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM over voltage is detected 1h = VM over voltage is detected |
5 | RESERVED | R-0 | 0h | Reserved |
4 | CP_UV | R | 0h | Charge pump under voltage fault status. This bit is not auto cleared even when retry is enabled in UVP_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No charge pump under voltage is detected 1h = Charge pump under voltage is detected |
3 | RESERVED | R-0 | 0h | Reserved |
2 | RESERVED | R | 0h | Reserved |
1 | VM_UV | R-0 | 0h | VM under voltage fault status. This bit is not auto cleared even when retry is enabled in UVP_MODE. Can be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM under voltage is detected 1h = VM under voltage is detected |
0 | RESERVED | R | 0h | Reserved |
DRV_STS is shown in Figure 8-32 and described in Table 8-15.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OCPC_HS | OCPB_HS | OCPA_HS | RESERVED | OCPC_LS | OCPB_LS | OCPA_LS |
R-0-0h | R-0h | R-0h | R-0h | R-0-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-7 | RESERVED | R-0 | 0h | Reserved |
6 | OCPC_HS | R | 0h | Over current status on high-side MOSFET of OUTC. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on high-side MOSFET of OUTC 1h = Over current detected on high-side MOSFET of OUTC |
5 | OCPB_HS | R | 0h | Over current status on high-side MOSFET of OUTB. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on high-side MOSFET of OUTB 1h = Over current detected on high-side MOSFET of OUTB |
4 | OCPA_HS | R | 0h | Over current status on high-side MOSFET of OUTA. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on high-side MOSFET of OUTA 1h = Over current detected on high-side MOSFET of OUTA |
3 | RESERVED | R-0 | 0h | Reserved |
2 | OCPC_LS | R | 0h | Over current status on low-side MOSFET of OUTC. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on low-side MOSFET of OUTC 1h = Over current detected on low-side MOSFET of OUTC |
1 | OCPB_LS | R | 0h | Over current status on low-side MOSFET of OUTB. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on low-side MOSFET of OUTB 1h = Over current detected on low-side MOSFET of OUTB |
0 | OCPA_LS | R | 0h | Over current status on low-side MOSFET of OUTA. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No over current detected on low-side MOSFET of OUTA 1h = Over current detected on low-side MOSFET of OUTA |
SYSIF_STS is shown in Figure 8-33 and described in Table 8-16.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OTPLD_ERR | RESERVED | SPI_PARITY | BUS_CNT | FRM_ERR | ||
R-0-0h | R-0h | R-0-0h | R-0h | R-0h | R-0h | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-5 | RESERVED | R-0 | 0h | Reserved |
4 | OTPLD_ERR | R | 0h | OTP parity error during load
0h = No OTP read error is detected 1h = OTP read error is detected |
3 | RESERVED | R-0 | 0h | Reserved |
2 | SPI_PARITY | R | 0h | SPI parity error
0h = No SPI Parity Error is detected 1h = SPI Parity Error is detected |
1 | BUS_CNT | R | 0h | SPI bus contention error
0h = No SPI Bus Contention Error is detected 1h = SPI Bus Contention Error is detected |
0 | FRM_ERR | R | 0h | SPI frame error
0h = No SPI Frame Error is detected 1h = SPI Frame Error is detected |
FLT_MODE is shown in Figure 8-34 and described in Table 8-17.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | VMUV_WARN_MODE | OVP_MODE | RESERVED | |||
R/W-0h | R-0-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SPIFLT_MODE | OCP_MODE | UVP_MODE | OTF_MODE | ||||
R/W-0h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-13 | RESERVED | R-0 | 0h | Reserved |
12-11 | VMUV_WARN_MODE | R/W | 0h | VM under voltage warning fault mode
0h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms) 1h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms) 2h = Report on nFAULT, latch into status register, no action on pre-driver 3h = Disabled |
10-9 | OVP_MODE | R/W | 0h | Over voltage protection fault mode
0h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms) 1h = Report on nFAULT, latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms) 2h = Reserved 3h = Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | SPIFLT_MODE | R/W | 0h | SPI fault mode
0h = Report on nFAULT, latch into status register, no action on pre-driver 1h = Disabled |
6-4 | OCP_MODE | R/W | 1h | Over current protection fault mode
0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms) 1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms) 2h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, no auto recovery, wait for CLR_FLT 3h = Report on nFAULT, Latch into status register, No action on pre-driver 4h = Reserved 5h = Reserved 6h = Reserved 7h = Reserved |
3-2 | UVP_MODE | R/W | 1h | Under voltage protection fault mode
0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with slow retry time (in ms) 1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recovery with fast retry time (in ms) 2h = Reserved 3h = Reserved |
1-0 | OTF_MODE | R/W | 1h | Over temperature fault mode
0h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recover with Slow Retry time (in ms) 1h = Report on nFAULT, Latch into status register, pre-driver Hi-Z, auto recover with Fast Retry time (in ms) 2h = Reserved 3h = Reserved |
SYSF_CTRL is shown in Figure 8-35 and described in Table 8-18.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | DNRDY_EN | OTW_FET_EN | RESERVED | |||
R/W-0h | R-0-0h | R/W-1h | R/W-0h | R/W-1h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VMUV_WARN_EN | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |
R/W-0h | R/W-1h | R-0-0h | R/W-1h | R-0-0h | R/W-1h | R/W-1h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-11 | RESERVED | R-0 | 0h | Reserved |
10 | DNRDY_EN | R/W | 1h | Device not ready fault enable
0h = Device not ready fault is disabled 1h = Device not ready fault is enabled |
9 | OTW_FET_EN | R/W | 0h | FET over temperature warning fault enable
0h = FET over temperature warning is disabled 1h = FET over temperature warning is enabled |
8 | RESERVED | R/W | 1h | Reserved |
7 | VMUV_WARN_EN | R/W | 0h | VM under voltage warn fault enable
0h = VM under voltage warning fault is disabled 1h = VM under voltage warning fault is enabled |
6 | RESERVED | R/W | 1h | Reserved |
5 | RESERVED | R-0 | 0h | Reserved |
4 | RESERVED | R/W | 1h | Reserved |
3-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 1h | Reserved |
0 | RESERVED | R/W | 1h | Reserved |
DRVF_TCTRL is shown in Figure 8-36 and described in Table 8-19.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | RESERVED | |||||
R/W-0h | R-0-0h | R/W-1h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OCP_DEG | OCP_TBLANK | VMUV_WARN_TDG | ||||
R/W-1h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-10 | RESERVED | R-0 | 0h | Reserved |
9-8 | RESERVED | R/W | 1h | Reserved |
7-6 | RESERVED | R/W | 1h | Reserved |
5-4 | OCP_DEG | R/W | 1h | OCP deglitch time
0h = 0.3 µs 1h = 0.6 µs 2h = 0.9 µs 3h = 1.2 µs |
3-2 | OCP_TBLANK | R/W | 1h | OCP blanking time
0h = 0.3 µs 1h = 0.7 µs 2h = 2 µs 3h = 1.2 µs |
1-0 | VMUV_WARN_TDG | R/W | 1h | VM under voltage warning deglitch time
0h = 0.3 µs 1h = 0.6 µs 2h = 0.9 µs 3h = 2 µs |
FLT_TCTRL is shown in Figure 8-37 and described in Table 8-20.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R/W-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SLOW_TRETRY | FAST_TRETRY | |||||
R-0-0h | R/W-0h | R/W-3h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-4 | RESERVED | R-0 | 0h | Reserved |
3-2 | SLOW_TRETRY | R/W | 0h | Retry time (typical) for slow recovery from fault condition
0h = 0.5s 1h = 1s 2h = 2s 3h = 5s |
1-0 | FAST_TRETRY | R/W | 3h | Retry time (typical) for fast recovery from fault condition
0h = 0.5ms 1h = 1ms 2h = 2ms 3h = 5ms |
FLT_CLR is shown in Figure 8-38 and described in Table 8-21.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | ||||||
R/W-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FLT_CLR | ||||||
R-0-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | RESERVED | R/W | 0h | Reserved |
14-1 | RESERVED | R-0 | 0h | Reserved |
0 | FLT_CLR | W | 0h | Clear latched faults
0h = No clear fault command is issued 1h = To clear the latched fault bits. This bit automatically resets after being written. |
VMUV_WARN_THR is shown in Figure 8-39 and described in Table 8-22.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R/W-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VMUV_WARN_RTH | VMUV_WARN_FTH | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-8 | RESERVED | R-0 | 0h | Reserved |
7-4 | VMUV_WARN_RTH | R/W | 0h | VM under voltage warning rising threshold
0h = 5.62V 1h = 6.25V 2h = 6.87V 3h = 7.5V 4h = 8.12V 5h = 8.75V 6h = 9.37V 7h = 10.00V 8h = 10.62V 9h = 11.25V Ah = 11.87V Bh = 12.5V Ch = 13.75V Dh = 15.00V Eh = 16.25V Fh = 17.5V |
3-0 | VMUV_WARN_FTH | R/W | 0h | VM under voltage warning falling threshold
0h = 5.4V 1h = 6.0V 2h = 6.6V 3h = 7.2V 4h = 7.8V 5h = 8.4V 6h = 9.0V 7h = 9.6V 8h = 10.2V 9h = 10.8V Ah = 11.4V Bh = 12.0V Ch = 13.2V Dh = 14.4V Eh = 15.6V Fh = 16.8V |
PWM_CTRL is shown in Figure 8-40 and described in Table 8-23.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R/W-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SSC_DIS | PWM_MODE | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-3 | RESERVED | R-0 | 0h | Reserved |
2 | SSC_DIS | R/W | 0h | Disable SSC on oscillator
0h = SSC enabled 1h = SSC disabled |
1-0 | PWM_MODE | R/W | 0h | PWM mode selection
0h = 6x mode 1h = 6x direct mode 2h = 3x mode 3h = 3x direct mode |
DRV_CTRL is shown in Figure 8-41 and described in Table 8-24.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | DLY_TARGET | |||||
R/W-0h | R-0-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DLYCMP_EN | RESERVED | SLEW_RATE | |||||
R/W-0h | R-0-0h | R/W-3h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | RESERVED | R-0 | 0h | Reserved |
11-8 | DLY_TARGET | R/W | 0h | Delay Target : DLY_TARGET * 0.2µs |
7 | DLYCMP_EN | R/W | 0h | Driver Delay Compensation enable
0h = Delay compensation disabled 1h = Delay compensation enabled |
6-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | SLEW_RATE | R/W | 3h | Slew rate settings
0h = Slew rate is 25 V/µs 1h = Slew rate is 50 V/µs 2h = Slew rate is 125 V/µs 3h = Slew rate is 200 V/µs |
CSA_CTRL is shown in Figure 8-42 and described in Table 8-25.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | RESERVED | ||||||
R/W-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_EN | RESERVED | CSA_GAIN | ||||
R-0-0h | R/W-1h | R-0-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-4 | RESERVED | R-0 | 0h | Reserved |
3 | CSA_EN | R/W | 1h | Enable CSA
0h = CSA is disabled 1h = CSA is enabled |
2 | RESERVED | R-0 | 0h | Reserved |
1-0 | CSA_GAIN | R/W | 0h | CSA Gain settings
0h = CSA gain is 0.25 V/A 1h = CSA gain is 0.5 V/A 2h = CSA gain is 1 V/A 3h = CSA gain is 2 V/A |
SYS_CTRL is shown in Figure 8-43 and described in Table 8-26.
Return to the Summary Table.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PARITY | WRITE_KEY | RESERVED | RESERVED | RESERVED | |||
R/W-0h | W-5h | R-0-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG_LOCK | SPI_PEN | RESERVED | RESERVED | RESERVED | |||
R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | PARITY | R/W | 0h | Parity Bit if SPI_PEN is set to '1' otherwise reserved |
14-12 | WRITE_KEY | W | 5h | 0x5 : Write Key specific to this register. |
11-10 | RESERVED | R-0 | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | REG_LOCK | R/W | 0h | Register Lock Bit
0h = Registers Unlocked 1h = Registers Locked |
6 | SPI_PEN | R/W | 0h | Parity Enable for SPI
0h = Parity Disabled 1h = Parity Enabled |
5-4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 1h | Reserved |
2-0 | RESERVED | R/W | 0h | Reserved |