SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
After an OCP event in this mode, all MOSFETs are in Hi-Z and the nFAULT pin is driven low. The FAULT, OCP bits (in DEV_STS register) and corresponding FETs' OCP bits (in DRV_STS register) are set to 1b. Normal operation resumes (pre-driver operation, FAULT, OCP, corresponding FETs' OCP bits set to 0b and the nFAULT pin is released) when a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).