SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
No protective action occurs after an OCP event in this mode. The over current event is reported by driving the nFAULT pin low and setting the FAULT, OCP bits (in DEV_STS register) and corresponding FETs' OCP bits (in DRV_STS register) to 1b. DRV8317 continues to operate as usual. The external controller manages the over current condition by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, OCP, and corresponding FETs' OCP bits are set to 0b) when a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).