SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
In the event of a SPI transaction fault (parity, frame or bus contention error), if SPLIFLT_MODE is set to 0b, nFAULT is driven low, FAULT, SPIFLT bits (in DEV_STS register) and SPI_PARITY/ BUS_CNT/ FRM_ERR bits (in SYSIF_STS register) are set to 1b. DRV8317 continues to operate as usual. The external controller manages the SPI fault event by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, SPIFLT, and SPI_PARITY/ BUS_CNT/ FRM_ERR bits are set to 0b) when a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse (tRST).
If SPIFLT_MODE is set to 1b, SPI fault is disabled and reporting (nFAULT, status register bits) does not happen on a SPI fault event.