SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
In the case of latched faults, DRV8317 turns off the MOSFETs (Hi-Z) and the motor coasts to a stop.
When the fault condition clears, the device can go to the operating state again by either setting the FLT_CLR bit to 1b in the SPI variant or by issuing a reset pulse on the nSLEEP pin in the hardware variant. The nSLEEP reset pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset pulse has no effect on any of the regulators, device settings, or other functional blocks.