SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
The hardware variant (DRV8317H) replaces the four SPI pins with three resistor-configurable pins, namely, GAIN, SLEW and MODE (one of the four SPI pins is NC in hardware variant).
PWM control mode, CSA gain and driver output slew rate can be adjusted on the hardware interface by tying the respective pins to AGND, AVDD, pulling down to AGND with a 47-kΩ resistor or by leaving the pin floating (Hi-Z). In DRV8317H, fault conditions are reported on the nFAULT pin, but detailed fault information is not available.
For more information on the hardware interface, see Section 8.3.9.
Configuration | GAIN | SLEW | MODE |
---|---|---|---|
Pin tied to AGND | 0.25-V/A | 25-V/µs | 6x PWM mode |
Pin pulled to AGND via 47-kΩ | 0.5-V/A | 50-V/µs | 6x PWM mode |
Pin floating (Hi-Z) | 1-V/A | 125-V/µs | 3x PWM mode |
Pin tied to AVDD | 2-V/A | 200-V/µs | 3x PWM mode |