SLVSGT3 December 2022 DRV8317
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES | ||||||
IVMQ | VM sleep mode current | VVM = 12 V, nSLEEP = 0, TA = 25 °C | 1.7 | 3 | µA | |
nSLEEP = 0, TA = 125 °C | 10 | µA | ||||
IVMS | VM standby mode current | VVM = 12 V, nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF', TA = 25 °C | 8 | 10 | mA | |
nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF' | 8 | 10 | mA | |||
IVM | VM operating mode current | VVM = 12 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C | 10 | 12 | mA | |
VVM = 12 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C | 10 | 14 | mA | |||
nSLEEP =1, fPWM = 25 kHz | 10 | 12 | mA | |||
nSLEEP =1, fPWM = 200 kHz | 10 | 15 | mA | |||
VAVDD | Analog regulator voltage | VVM ≥ 6V, VVIN_AVDD ≥ 6V, 0 mA ≤ IAVDD ≤ 80 mA | 3.15 | 3.3 | 3.45 | V |
VAVDD | Analog regulator voltage | 4.5V ≤ VVM < 6V, 4.5V ≤ VVIN_AVDD < 6V, 0 mA ≤ IAVDD ≤ 80 mA | 3.15 | 3.3 | 3.45 | V |
IAVDD | Analog regulator external load | 4.5V ≤ VVM < 6V, 4.5V ≤ VVIN_AVDD < 6V | 80 | mA | ||
IAVDD | Analog regulator external load | VVM ≥ 6V, VVIN_AVDD ≥ 6V | 80 | mA | ||
IAVDD_LIM | Analog regulator current limit | VAVDD ≥ 2.7V, soft short to GND | 100 | 125 | 150 | mA |
CAVDD | Capacitance for AVDD | External load IAVDD = 0 mA | 0.5 | 2.2 | 7.05 | uF |
External load 0mA ≤ IAVDD ≤ 80 mA | 2.35 | 4.7 | 7.05 | uF | ||
VCP | Charge pump regulator voltage | 4.5V ≤ VVM < 6V, CP with respect to VM | 3 | 5 | 5.5 | V |
VCP | Charge pump regulator voltage | VVM ≥ 6V, CP with respect to VM | 4.5 | 5 | 5.5 | V |
tWAKE | Wakeup time | VVM > VUVLO, nSLEEP = 1 to output ready | 1 | 3 | ms | |
tWAKE_CSA | Wakeup time for CSA | VCSAREF > VCSAREF_UV to SOx ready, when nSLEEP = 1 | 30 | µs | ||
tSLEEP | Turn-off time | nSLEEP = 0 to driver tri-stated | 100 | 200 | µs | |
tRST | Reset Pulse time | nSLEEP = 0 period to reset faults | 15 | 50 | µs | |
FOUR-LEVEL INPUTS (GAIN, MODE, SLEW) | ||||||
VL1 | Input mode 1 voltage | Tied to AGND | 0 | 0.2*AVDD | V | |
VL2 | Input mode 2 voltage | 47 kΩ ± 5% tied to AGND | 0.27*AVDD | 0.4*AVDD | 0.545*AVDD | V |
VL3 | Input mode 3 voltage | Hi-Z | 0.606*AVDD | 0.757*AVDD | 0.909*AVDD | V |
VL4 | Input mode 4 voltage | Tied to AVDD | 0.94*AVDD | AVDD | V | |
RPU | Input pullup resistance | To AVDD | 48 | kΩ | ||
RPD | Input pulldown resistance | To AGND | 160 | kΩ | ||
DRIVER OUTPUTS | ||||||
RDS(ON) | Total MOSFET on resistance (High-side + Low-side) | VVM ≥ 6 V, IOUT = 1 A, TJ = 25°C, includes bond wire and metallization resistance | 130 | 157 | mΩ | |
VVM ≥ 6 V, IOUT = 1 A, TJ = 125°C, across process, includes bond wire and metallization resistance | 180 | 221.5 | mΩ | |||
RDS(ON) | Total MOSFET on resistance (High-side + Low-side) | 4.5 V ≤ VVM < 6 V, IOUT = 1 A, TJ = 25°C, includes bond wire and metallization resistance | 155 | 210 | mΩ | |
4.5 V ≤ VVM < 6 V, IOUT = 1 A, TJ = 125°C,across process, includes bond wire and metallization resistance | 225 | 290 | mΩ | |||
SR_RISE | Phase pin slew rate switching low to high (Rising from 20 % to 80 % of VM) | VVM = 12V, SLEW_RATE = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) | 13.75 | 25 | 36.25 | V/µs |
VVM = 12V, SLEW_RATE = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) | 27.5 | 50 | 72.5 | V/µs | ||
VVM = 12V, SLEW_RATE = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) | 62.5 | 125 | 187.5 | V/µs | ||
VVM = 12V, SLEW_RATE = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) | 80 | 200 | 320 | V/µs | ||
SR_FALL | Phase pin slew rate switching high to low (Falling from 80 % to 20 % of VM) | VVM = 12V, SLEW_RATE = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) | 13.75 | 25 | 48 | V/µs |
VVM = 12V, SLEW_RATE = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) | 27.5 | 50 | 72.5 | V/µs | ||
VVM = 12V, SLEW_RATE = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) | 62.5 | 125 | 187.5 | V/µs | ||
VVM = 12V, SLEW_RATE = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) | 80 | 200 | 320 | V/µs | ||
ILEAK | Leakage current OUTx | VVM = VOUTx = 20 V, Standby State | 0.7 | 2 | mA | |
ILEAK | Leakage current OUTx | VOUTx = 0 V, Standby State | -50 | -10 | µA | |
tDEAD | Dead time (high to low / low to high) | VVM = 12V, SLEW_RATE = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) | 575 | 1500 | ns | |
VVM = 12V, SLEW_RATE = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) | 325 | 750 | ns | |||
VVM = 12V, SLEW_RATE = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) | 250 | 600 | ns | |||
VVM = 12V, SLEW_RATE = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) | 250 | 600 | ns | |||
tPD | Propagation delay (high-side / low-side ON/OFF) | INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) | 1300 | 1750 | ns | |
INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) | 800 | 1050 | ns | |||
INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) | 450 | 600 | ns | |||
INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) | 425 | 500 | ns | |||
tMIN_PULSE | Minimum output pulse width | SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) | 500 | ns | ||
CURRENT SENSE AMPLIFIER | ||||||
GCSA | Current sense gain | CSA_GAIN = 00b (SPI Variant) or GAIN pin tied to AGND (HW Variant) | 0.25 | V/A | ||
CSA_GAIN = 01b (SPI Variant) or GAIN pin to 47 kΩ +/- 5% tied to AGND (HW Variant) | 0.5 | V/A | ||||
CSA_GAIN = 10b (SPI Variant) or GAIN pin to Hi-Z (HW Variant) | 1 | V/A | ||||
CSA_GAIN = 11b (SPI Variant) or GAIN pin tied to AVDD (HW Variant) | 2 | V/A | ||||
GCSA_ERR | Current sense gain error | TA = 25°C, IPHASE ≤ 2.5 A | –3 | 3 | % | |
GCSA_ERR | Current sense gain error | TA = 25°C, 2.5 A < IPHASE ≤ 4 A | –3.5 | 3.5 | % | |
GCSA_ERR | Current sense gain error | TA = 25°C, 4 A < IPHASE ≤ 5 A | –3.5 | 4.5 | % | |
GCSA_ERR | Current sense gain error | IPHASE ≤ 2.5 A | –4.5 | 4.5 | % | |
GCSA_ERR | Current sense gain error | 2.5 A < IPHASE ≤ 4 A | –5 | 6 | % | |
GCSA_ERR | Current sense gain error | 4A < IPHASE ≤ 5 A | –5 | 8 | % | |
IMATCH | Current sense gain error matching between phases A, B and C | TJ = 25°C | –3 | 3 | % | |
–5 | 5 | % | ||||
FSPOS | Full scale positive current measurement | 5 | A | |||
FSNEG | Full scale negative current measurement | –5 | A | |||
VLINEAR | SOX output voltage linear range | 0.25 | VREF – 0.25 | V | ||
IOFFSET_RT | Current sense offset low side current input (Room Temperature) | TJ = 25°C, Phase current = 0 A, GCSA = 0.25 V/A | –100 | 100 | mA | |
TJ = 25°C, Phase current = 0 A, GCSA = 0.5 V/A | –50 | 50 | mA | |||
TJ = 25°C, Phase current = 0 A, GCSA = 1 V/A | –30 | 30 | mA | |||
TJ = 25°C, Phase current = 0 A, GCSA = 2 V/A | –30 | 30 | mA | |||
IOFFSET | Current sense offset low side current input | Phase current = 0 A, GCSA = 0.25 V/A | –140 | 140 | mA | |
Phase current = 0 A, GCSA = 0.5 V/A | –70 | 70 | mA | |||
Phase current = 0 A, GCSA = 1 V/A | –50 | 50 | mA | |||
Phase current = 0 A, GCSA = 2 V/A | –50 | 50 | mA | |||
tSET | Settling time to ±1%, 30 pF | Step on SOX = 1.2 V, GCSA = 0.25 V/A | 1 | μs | ||
Step on SOX = 1.2 V, GCSA = 0.5 V/A | 1 | μs | ||||
Step on SOX = 1.2 V, GCSA = 1 V/A | 1 | μs | ||||
Step on SOX = 1.2 V, GCSA = 2 V/A | 1 | μs | ||||
VDRIFT | Drift offset | Phase current = 0 A | –360 | 360 | µA/℃ | |
ICSAREF | CSAREF input current | VREF = 3.0 V | 12 | 20 | µA | |
PROTECTION CIRCUITS | ||||||
VOVP | Supply overvoltage protection (OVP) | VM rising | 21 | 22 | 23 | V |
VM falling | 20 | 21 | 22 | V | ||
VOVP_HYS | Supply overvoltage protection hysteresis | Falling to rising threshold | 900 | 1000 | 1200 | mV |
tOVP | Supply overvoltage protection deglitch time | 3 | 5 | 7 | µs | |
VUVLO | Supply undervoltage lockout (UVLO) | VM rising | 4.25 | 4.4 | 4.61 | V |
VM falling | 4.1 | 4.2 | 4.35 | V | ||
VUVLO_HYS | Supply undervoltage lockout hysteresis | Rising to falling threshold | 140 | 210 | 350 | mV |
tUVLO | Supply undervoltage lockout deglitch time | 3 | 5 | 7 | µs | |
VVMUV_WARN_RISE | Supply (VM) undervoltage warning, rising | VM rising, VMUV_WARN_RISE = 0000b | 5.4 | 5.62 | 6 | V |
VM rising, VMUV_WARN_RISE = 0001b | 6 | 6.25 | 6.6 | V | ||
VM rising, VMUV_WARN_RISE = 0010b | 6.6 | 6.87 | 7.25 | V | ||
VM rising, VMUV_WARN_RISE = 0011b | 7.15 | 7.5 | 7.95 | V | ||
VM rising, VMUV_WARN_RISE = 0100b | 7.8 | 8.12 | 8.6 | V | ||
VM rising, VMUV_WARN_RISE = 0101b | 8.4 | 8.75 | 9.3 | V | ||
VM rising, VMUV_WARN_RISE = 0110b | 9 | 9.37 | 9.9 | V | ||
VM rising, VMUV_WARN_RISE = 0111b | 9.6 | 10 | 10.6 | V | ||
VM rising, VMUV_WARN_RISE = 1000b | 10.2 | 10.62 | 11.2 | V | ||
VM rising, VMUV_WARN_RISE = 1001b | 10.8 | 11.25 | 11.9 | V | ||
VM rising, VMUV_WARN_RISE = 1010b | 11.35 | 11.87 | 12.55 | V | ||
VM rising, VMUV_WARN_RISE = 1011b | 11.95 | 12.5 | 13.15 | V | ||
VM rising, VMUV_WARN_RISE = 1100b | 13.2 | 13.75 | 14.5 | V | ||
VM rising, VMUV_WARN_RISE = 1101b | 14.3 | 15.00 | 15.9 | V | ||
VM rising, VMUV_WARN_RISE = 1110b | 15.5 | 16.25 | 17.1 | V | ||
VM rising, VMUV_WARN_RISE = 1111b | 16.7 | 17.5 | 18.6 | V | ||
VVMUV_WARN_FALL | Supply (VM) undervoltage warning, falling | VM falling, VMUV_WARN_FALL = 0000b | 5.1 | 5.4 | 5.75 | V |
VM falling, VMUV_WARN_FALL = 0001b | 5.7 | 6.0 | 6.3 | V | ||
VM falling, VMUV_WARN_FALL = 0010b | 6.25 | 6.6 | 6.95 | V | ||
VM falling, VMUV_WARN_FALL = 0011b | 6.8 | 7.2 | 7.6 | V | ||
VM falling, VMUV_WARN_FALL = 0100b | 7.4 | 7.8 | 8.2 | V | ||
VM falling VMUV_WARN_FALL = 0101b | 7.95 | 8.4 | 8.85 | V | ||
VM falling, VMUV_WARN_FALL = 0110b | 8.5 | 9.0 | 9.5 | V | ||
VM falling, VMUV_WARN_FALL = 0111b | 9.05 | 9.6 | 10.15 | V | ||
VM falling, VMUV_WARN_FALL = 1000b | 9.7 | 10.2 | 10.7 | V | ||
VM falling, VMUV_WARN_FALL = 1001b | 10.15 | 10.8 | 11.4 | V | ||
VM falling, VMUV_WARN_FALL = 1010b | 10.75 | 11.4 | 12 | V | ||
VM falling, VMUV_WARN_FALL = 1011b | 11.3 | 12.0 | 12.6 | V | ||
VM falling, VMUV_WARN_FALL = 1100b | 12.5 | 13.2 | 13.8 | V | ||
VM falling, VMUV_WARN_FALL = 1101b | 13.5 | 14.4 | 15.3 | V | ||
VM falling, VMUV_WARN_FALL = 1110b | 14.7 | 15.6 | 16.4 | V | ||
VM falling, VMUV_WARN_FALL = 1111b | 15.9 | 16.8 | 17.8 | V | ||
tVMUV_WARN_DG | Supply undervoltage warning deglitch time | VMUV_TDG = 00b | 0.1 | 0.3 | 0.45 | µs |
VMUV_TDG = 01b | 0.35 | 0.6 | 0.8 | µs | ||
VMUV_TDG = 10b | 0.55 | 0.9 | 1.35 | µs | ||
VMUV_TDG = 11b | 1.4 | 2 | 2.5 | µs | ||
tVMUV_WARN_DG | Supply undervoltage warning deglitch time (HW variant) | 0.35 | 0.6 | 0.8 | µs | |
VVIN_AVDD_UV | AVDD supply input undervoltage lockout (VIN_AVDD_UV) | VIN_AVDD rising | 4.25 | 4.4 | 4.61 | V |
VIN_AVDD falling | 4.1 | 4.2 | 4.35 | V | ||
VVIN_AVDD_UV_HYS | Supply undervoltage lockout hysteresis | Rising to falling threshold | 140 | 210 | 350 | mV |
VCPUV | Charge pump undervoltage lockout (above VM) | Supply rising | 2.64 | 2.8 | 2.95 | V |
Supply falling | 2.35 | 2.6 | 2.7 | V | ||
VCPUV_HYS | Charge pump undervoltage lockout hysteresis | Rising to falling threshold | 160 | 210 | 245 | mV |
tCPUV | Charge pump undervoltage lockout deglitch time | 3 | 5 | 7 | µs | |
VAVDD_UV | Analog regulator undervoltage lockout | Supply rising | 2.7 | 2.8 | 2.9 | V |
Supply falling | 2.6 | 2.7 | 2.8 | V | ||
VAVDD_UV_HYS | Analog regulator undervoltage lockout hysteresis | Rising to falling threshold | 80 | 100 | 150 | mV |
IOCP | Overcurrent protection trip point | 6 | 9.5 | 12 | A | |
tBLANK(1) | Overcurrent protection blanking time | OCP_TBLANK = 00b | 0.15 | 0.3 | 0.45 | µs |
OCP_TBLANK = 01b | 0.45 | 0.7 | 0.85 | µs | ||
OCP_TBLANK = 10b | 0.7 | 1 | 1.25 | µs | ||
OCP_TBLANK = 10b | 0.9 | 1.2 | 1.5 | µs | ||
tBLANK(1) | Overcurrent protection blanking time (HW Variant) | 0.45 | 0.7 | 0.85 | µs | |
tOCP(1) | Overcurrent protection deglitch time | OCP_DEG = 00b | 0.1 | 0.3 | 0.45 | µs |
OCP_DEG = 01b | 0.35 | 0.6 | 0.85 | µs | ||
OCP_DEG = 10b | 0.6 | 0.9 | 1.25 | µs | ||
OCP_DEG = 11b | 0.8 | 1.2 | 1.5 | µs | ||
tOCP(1) | Overcurrent protection deglitch time (HW Variant) | 0.35 | 0.6 | 0.85 | µs | |
tRETRY | Overcurrent protection retry time | FAST_TRETRY = 00b | 0.35 | 0.5 | 0.7 | ms |
FAST_TRETRY = 01b | 0.75 | 1 | 1.3 | ms | ||
FAST_TRETRY = 10b | 1.65 | 2 | 2.45 | ms | ||
FAST_TRETRY = 11b | 4.35 | 5 | 5.85 | ms | ||
tRETRY | Overcurrent protection retry time | SLOW_TRETRY = 00b | 350 | 500 | 700 | ms |
SLOW_TRETRY = 01b | 750 | 1000 | 1300 | ms | ||
SLOW_TRETRY = 10b | 1650 | 2000 | 2450 | ms | ||
SLOW_TRETRY = 11b | 4350 | 5000 | 5850 | ms | ||
tRETRY | Overcurrent protection retry time (HW Variant) | 4.35 | 5 | 5.85 | ms | |
TOTW_FET | Overtemperature warning threshold (FET) | Die temperature (TJ) Rising | 110 | 125 | 140 | °C |
TOTW_HYS_FET | Overtemperature warning hysteresis (FET) | Die temperature (TJ) | 15 | 20 | 25 | °C |
TOTS_FET | Overtemperature shutdown threshold (FET) | Die temperature (TJ) Rising | 145 | 160 | 175 | °C |
TOTS_HYS_FET | Overtemperature shutdown hysteresis (FET) | Die temperature (TJ) | 14 | 20 | 25 | °C |
TOTS_LDO | Overtemperature shutdown threshold (LDO) | Die temperature (TJ) Rising | 145 | 160 | 175 | °C |
TOTS_HYS_LDO | Overtemperature shutdown hysteresis (LDO) | Die temperature (TJ) | 14 | 20 | 25 | °C |
LOGIC-LEVEL INPUTS (INHx, INLx, nSLEEP, SCLK, SDI) | ||||||
VIL | Input logic low voltage | nSLEEP | 0 | 0.7 | V | |
VIL | Input logic low voltage | SDI, INLx, INHx, SCLK | 0 | 0.65 | V | |
VIH | Input logic high voltage | nSLEEP | 1.7 | 5.5 | V | |
VIH | Input logic high voltage | SDI, INLx, INHx, SCLK | 1.5 | 3.6 | V | |
VHYS | Input logic hysteresis | nSLEEP | 200 | 600 | mV | |
VHYS | Input logic hysteresis | SDI, INLx, INHx, SCLK | 200 | 500 | mV | |
IIL | Input logic low current | nSLEEP, SDI, INLx, INHx, SCLK (Pin Voltage) = 0 V | –1 | 1 | µA | |
IIH | Input logic high current | nSLEEP (Pin Voltage) = 5V | 40 | µA | ||
Other pins, 3V ≤ VPIN (Pin Voltage) ≤ 3.6V | 30 | µA | ||||
RPD | Input pulldown resistance | nSLEEP | 150 | 300 | kΩ | |
SDI, SCLK, INHx, INLx | 150 | 300 | kΩ | |||
CID | Input capacitance | nSLEEP, SDI, SCLK, INHx, INLx | 30 | pF | ||
LOGIC-LEVEL INPUTS (nSCS) | ||||||
VIL | Input logic low voltage | 0 | 0.7 | V | ||
VIH | Input logic high voltage | 1.5 | 3.6 | V | ||
VHYS | Input logic hysteresis | 200 | 500 | mV | ||
IIL | Input logic low current | VPIN (Pin Voltage) = 0 V | 95 | µA | ||
IIH | Input logic high current | 3V ≤ VPIN (Pin Voltage) ≤ 3.6V | -1 | 1 | µA | |
RPU | Input pullup resistance | 35 | 48 | 75 | kΩ | |
CID | Input capacitance | 30 | pF | |||
OPEN-DRAIN OUTPUTS (nFAULT) | ||||||
VOL | Output logic low voltage | IOD = -5 mA | 0.4 | V | ||
IOH | Output logic high current | 3V ≤ VOD ≤ 3.6 V | –1 | 1 | µA | |
COD | Output capacitance | 30 | pF | |||
PUSH-PULL OUTPUTS (SDO) | ||||||
VOL | Output logic low voltage | IOP = -5 mA, 3V ≤ VAVDD ≤ 3.6V | 0 | 0.5 | V | |
VOH | Output logic high voltage | IOP = 5 mA, 3V ≤ VAVDD ≤ 3.6V | VAVDD - 0.5 | 3.6 | V | |
IOL | Output logic low current | VOP = 0 V | –1 | 1 | µA | |
IOH | Output logic high current | VOP = 5 V | –2 | 2 | µA | |
COD | Output capacitance | 30 | pF |