The DRV8328 family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The device generates the correct gate drive voltages using an internal charge pump and enhances the high-side MOSFETs using a bootstrap circuit. A trickle charge pump is included to support 100% duty cycle. The Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A sink. The DRV8328 can operate from a single power supply and supports a wide input supply range of 4.5 to 60 V.
The 6x and 3x PWM modes allow for simple interfacing to controller circuits. The device has integrated accurate 3.3-V LDO that can be used to power external controller and can be used as reference for CSA. The configuration settings for the device are configurable through hardware (H/W) pins.
A low-power sleep mode is provided to achieve low quiescent current by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, GVDD fault, MOSFET overcurrent, MOSFET short circuit, and overtemperature. Fault conditions are indicated on nFAULT pin.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8328ARUY | WQFN (28) | 4.00 mm × 4.00 mm |
DRV8328BRUY | WQFN (28) | 4.00 mm × 4.00 mm |
DRV8328CRUY | WQFN (28) | 4.00 mm × 4.00 mm |
DRV8328DRUY | WQFN (28) | 4.00 mm × 4.00 mm |
Changes from Revision B (March 2022) to Revision C (October 2022)
Changes from Revision A (February 2022) to Revision B (March 2022)
Changes from Revision * (December 2021) to Revision A (February 2022)
DEVICE | DEVICE VARIANT | Package | LDO output | DT pin and VDSLVL | PWM_MODE |
---|---|---|---|---|---|
DRV8328 | DRV8328A | 28-pin QFN (4.00 mm x 4.00 mm) |
Not Available | Available | 6x |
DRV8328B | 3x | ||||
DRV8328C | 3.3 V | Not Available | 6x | ||
DRV8328D | 3x |
PIN | TYPE | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO. | ||||
DRV8328A DRV8328B |
DRV8328C DRV8328D |
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AVDD | - | 19 | PWR-O | 3.3-V regulator output. Connect a X5R or X7R, 1-µF, >6.3-V ceramic capacitor between the AVDD and GND pins. This regulator can source up to 80 mA externally. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin. | |
BSTA | 5 | 5 | O | Bootstrap output pin. Connect capacitor between BSTA and SHA | |
BSTB | 9 | 9 | O | Bootstrap output pin. Connect capacitor between BSTB and SHB | |
BSTC | 13 | 13 | O | Bootstrap output pin. Connect capacitor between BSTC and SHC | |
CPH | 3 | 3 | PWR | Charge pump switching node. Connect a X5R or X7R, PVDD-rated ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin. | |
CPL | 2 | 2 | PWR | ||
DT | 27 | - | I | Gate drive deadtime setting. Connect a resistor of value between 10 kΩ to 390 kΩ between DT and GND to adjust deadtime between 100 ns to 2000 ns. If pin is left floating or connected to GND fixed value of 55 ns deadtime is inserted. | |
DRVOFF | - | 18 | I | Independent driver shutdown path. Pulling DRVOFF high turns off all external MOSFETs by putting the gate drivers into the pull-down state. This signal bypasses and overrides the digital core of the DRV8328. | |
GHA | 7 | 7 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GHB | 11 | 11 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GHC | 15 | 15 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GLA | 8 | 8 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GLB | 12 | 12 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GLC | 16 | 16 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GND | 28 | 28 | PWR | Device ground. | |
GVDD | 4 | 4 | PWR-O | Gate driver power supply output. Connect a X5R or X7R, 30-V rated ceramic ≥ 10-uF local capacitance between the GVDD and GND pins. TI recommends a capacitor value of >10x CBSTx and voltage rating at least twice the normal operating voltage of the pin. | |
INHA | 20 | 22 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INHB | 19 | 21 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INHC | 18 | 20 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INLA | 23 | 25 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
INLB | 22 | 24 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
INLC | 21 | 23 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
LSS | 17 | 17 | PWR | Low side source pin, connect all sources of the external low-side MOSFETs here. This pin is the sink path for the low-side gate driver. | |
nFAULT | 24 | 27 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor to 3.3V to 5.0V. | |
nSLEEP | 25 | 26 | I | Sleep mode entry pin. When this pin is pulled logic low the device goes to a low-power sleep mode. An 1 to 1.2-µs low pulse can be used to reset fault conditions without entering sleep mode . | |
PVDD | 1 | 1 | PWR | Gate driver power supply input. Connect to the bridge power supply. Connect a X5R or X7R, 0.1-µF, >2x PVDD-rated ceramic and >10-uF local capacitance between the PVDD and GND pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the pin. | |
SHA | 6 | 6 | I/O | High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. | |
SHB | 10 | 10 | I/O | High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. | |
SHC | 14 | 14 | I/O | High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. | |
VDSLVL | 26 | - | I | VDS monitor trip point setting. | |
Thermal Pad | PWR | Must be connected to GND |
PWR = power, I = input, O = output, NC = no connection, OD = open-drain output