Minimize length and impedance of GHx, SHx, GLx, and SLx traces. Use as few vias
as possible to minimize parasitic inductance. It is also recommended to increase
these trace widths shortly after routing away from the device pin to minimize
parasitic resistance.
Keep BSTx capacitors close to their respective pins
Keep CPH/CPL flying capacitor as close to the device pins as possible
Keep PVDD capacitors close to PVDD pin
Keep VDRAIN capacitor close to VDRAIN pin to supply steady switching current for
the charge pump.
Additional bulk capacitance is required to bypass the high current path on the
external MOSFETs. This bulk capacitance should be placed such that it minimizes
the length of any high current paths through the external MOSFETs. The
connecting metal traces should be as wide as possible, with numerous vias
connecting PCB layers. These practices minimize inductance and let the bulk
capacitor deliver high current.
Connect SLx pins to MOSFET source, not directly to GND, for accurate VDS
detection.
Route SNx/SPx pins in parallel from the sense resistor to the device. Place
filtering components close to the device pins to minimize post-filter noise
coupling. Ensure that SNx/SPx stay separated from GND plane to achieve best CSA
accuracy.
The exposed pad is used for thermal dissipation, not electrical grounding, and
has a high-impedance connection to the GND/AGND pins. Therefore, it is
recommended to connect the exposed pad to the best thermal GND, and to connect
the GND/AGND pins to the MCU-reference GND.