SLVSHC7 December 2023 DRV8334
PRODUCTION DATA
In 6xPWM mode of DRV8334, high-side INHx and low-side INLx inputs operate independently, with an exception to prevent cross conduction when the high and low side of the same half-bridge are turned ON at same time. The device pulls high- and low- side gate outputs low to prevent shoot through condition of power stage and a fault STP_FLT is reported when high- and low-side inputs are logic high at the same time.
In 6xPWM mode, if SPI register bit DEADT_MODE is 0b and DEADT_MODE_6X is 00b, the device monitors INHx and INLx and inserts dead time if the period of INHx=INLx=low is shorter than tDEAD. Other than 6xPWM mode, dead time is always inserted regardless of the configuration.