SLVSE12A March 2018 – April 2019 DRV8343-Q1
PRODUCTION DATA.
Table 20 lists the memory-mapped registers for the control registers. All register offset addresses not listed in Table 20 should be considered as reserved locations and the register contents should not be modified.
The IC control registers are used to configure the device. Control registers are read and write capable.
Address | Register Name | Section |
---|---|---|
0x04 | IC1 Control | Go |
0x05 | IC2 Control | Go |
0x06 | IC3 Control | Go |
0x07 | IC4 Control | Go |
0x08 | IC5 Control | Go |
0x09 | IC6 Control | Go |
0x0A | IC7 Control | Go |
0x0B | IC8 Control | Go |
0x0C | IC9 Control | Go |
0x0D | IC10 Control | Go |
0x0E | IC11 Control | Go |
0x0F | IC12 Control | Go |
0x10 | IC13 Control | Go |
0x11 | IC14 Control | Go |