The DRV835xF family of devices are highly-integrated gate drivers for three-phase brushless DC (BLDC) motor applications. The device variants provide optional integrated current shunt amplifiers to support different motor control schemes.
The DRV835xF uses smart gate drive (SGD) architecture to decrease the number of external components that are typically necessary for MOSFET slew rate control and protection circuits. The SGD architecture also optimizes dead time to prevent shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects against gate short circuit conditions through VGS monitors. A strong gate pulldown circuit helps prevent unwanted dV/dt parasitic gate turn on events
Various PWM control modes (6x, 3x, 1x, and independent) are supported for simple interfacing to the external controller. These modes can decrease the number of outputs required of the controller for the motor driver PWM control signals. This family of devices also includes 1x PWM mode for simple sensored trapezoidal control of a BLDC motor by using an internal block commutation table.
(1)PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8350F | WQFN (32) | 5.00 mm × 5.00 mm |
DRV8353F | WQFN (40) | 6.00 mm × 6.00 mm |
Changes from Revision A (October 2020) to Revision B (August 2021)
DEVICE | VARIANT | SHUNT AMPLIFIERS | INTERFACE |
---|---|---|---|
DRV8350F | DRV8350FH | 0 | Hardware (H) |
DRV8350FS | SPI (S) | ||
DRV8353F | DRV8353FH | 3 | Hardware (H) |
DRV8353FS | SPI (S) |
PIN | TYPE(1) | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO. | ||||
DRV8350FH | DRV8350FS | ||||
CPH | 1 | 1 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. | |
CPL | 32 | 32 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. | |
DVDD | 29 | 29 | PWR | 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally. | |
ENABLE | 22 | 22 | I | Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs pulse can be used to reset fault conditions. | |
GHA | 5 | 5 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GHB | 12 | 12 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GHC | 13 | 13 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GLA | 7 | 7 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GLB | 10 | 10 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GLC | 15 | 15 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GND | 30 | 30 | PWR | Device primary ground. Connect to system ground. | |
IDRIVE | 19 | — | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. | |
INHA | 23 | 23 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INHB | 25 | 25 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INHC | 27 | 27 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INLA | 24 | 24 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
INLB | 26 | 26 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
INLC | 28 | 28 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
MODE | 18 | — | I | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. | |
NC | 21 | — | NC | No internal connection. This pin can be left floating or connected to system ground. | |
nFAULT | 17 | 17 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. | |
nSCS | — | 21 | I | Serial chip select. A logic low on this pin enables serial interface communication. | |
SCLK | — | 20 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. | |
SDI | — | 19 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. | |
SDO | — | 18 | OD | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. | |
SHA | 6 | 6 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
SHB | 11 | 11 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
SHC | 14 | 14 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
SLA | 8 | 8 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
SLB | 9 | 9 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
SLC | 16 | 16 | I | Low-side source sense input. Connect to the low-side power MOSFET source. | |
VCP | 4 | 4 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins. | |
VDRAIN | 3 | 3 | I | High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains. | |
VDS | 20 | — | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. | |
VGLS | 31 | 31 | PWR | 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins. | |
VM | 2 | 2 | PWR | Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins. |
PIN | TYPE(1) | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | NO. | ||||
DRV8353FH | DRV8353FS | ||||
AGND | 25 | 25 | PWR | Device analog ground. Connect to system ground. | |
CPH | 2 | 2 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. | |
CPL | 1 | 1 | PWR | Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. | |
DVDD | 38 | 38 | PWR | 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This regulator can source up to 10 mA externally. | |
ENABLE | 31 | 31 | I | Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. | |
GAIN | 30 | — | I | Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. | |
GND | 39 | 39 | PWR | Device power ground. Connect to system ground. | |
GHA | 6 | 6 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GHB | 15 | 15 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GHC | 16 | 16 | O | High-side gate driver output. Connect to the gate of the high-side power MOSFET. | |
GLA | 8 | 8 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GLB | 13 | 13 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
GLC | 18 | 18 | O | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. | |
IDRIVE | 28 | — | I | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. | |
INHA | 32 | 32 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INHB | 34 | 34 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INHC | 36 | 36 | I | High-side gate driver control input. This pin controls the output of the high-side gate driver. | |
INLA | 33 | 33 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
INLB | 35 | 35 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
INLC | 37 | 37 | I | Low-side gate driver control input. This pin controls the output of the low-side gate driver. | |
MODE | 27 | — | I | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. | |
nFAULT | 26 | 26 | OD | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. | |
nSCS | — | 30 | I | Serial chip select. A logic low on this pin enables serial interface communication. | |
SCLK | — | 29 | I | Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin. | |
SDI | — | 28 | I | Serial data input. Data is captured on the falling edge of the SCLK pin. | |
SDO | — | 27 | OD | Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor. | |
SHA | 7 | 7 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
SHB | 14 | 14 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
SHC | 17 | 17 | I | High-side source sense input. Connect to the high-side power MOSFET source. | |
SNA | 10 | 10 | I | Shunt amplifier input. Connect to the low-side of the current shunt resistor. | |
SNB | 11 | 11 | I | Shunt amplifier input. Connect to the low-side of the current shunt resistor. | |
SNC | 20 | 20 | I | Shunt amplifier input. Connect to the low-side of the current shunt resistor. | |
SOA | 23 | 23 | O | Shunt amplifier output. | |
SOB | 22 | 22 | O | Shunt amplifier output. | |
SOC | 21 | 21 | O | Shunt amplifier output. | |
SPA | 9 | 9 | I | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
SPB | 12 | 12 | I | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
SPC | 19 | 19 | I | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. | |
VCP | 5 | 5 | PWR | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins. | |
VDRAIN | 4 | 4 | I | High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains. | |
VDS | 29 | — | I | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. | |
VGLS | 40 | 40 | PWR | 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins. | |
VM | 3 | 3 | PWR | Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R, 0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins. | |
VREF | 24 | 24 | PWR | Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins. |
MIN | MAX | UNIT | |
---|---|---|---|
GATE DRIVER | |||
Power supply pin voltage (VM) | –0.3 | 80 | V |
Voltage differential between ground pins (AGND, BGND, DGND, PGND) | –0.3 | 0.3 | V |
MOSFET drain sense pin voltage (VDRAIN) | –0.3 | 102 | V |
MOSFET drain sense pin voltage slew rate (VDRAIN) | 0 | 2 | V/µs |
Charge pump pin voltage (CPH, VCP) | –0.3 | VVDRAIN + 16 | V |
Charge-pump negative-switching pin voltage (CPL) | –0.3 | VVDRAIN | V |
Low-side gate drive regulator pin voltage (VGLS) | –0.3 | 18 | V |
Internal logic regulator pin voltage (DVDD) | –0.3 | 5.75 | V |
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS) | –0.3 | 5.75 | V |
Continuous high-side gate drive pin voltage (GHx) | –5(2) | VVCP + 0.3 | V |
Transient 200-ns high-side gate drive pin voltage (GHx) | –10 | VVCP + 0.3 | V |
High-side gate drive pin voltage with respect to SHx (GHx) | –0.3 | 16 | V |
Continuous high-side source sense pin voltage (SHx) | –5(2) | 102 | V |
Continuous high-side source sense pin voltage (SHx) | –5(2) | VVDRAIN + 5 | V |
Transient 200-ns high-side source sense pin voltage (SHx) | –10 | VVDRAIN + 10 | V |
Continuous low-side gate drive pin voltage (GLx) | –1.0 | VVGLS + 0.3 | V |
Transient 200-ns low-side gate drive pin voltage (GLx) | –5.0 | VVGLS + 0.3 | V |
Gate drive pin source current (GHx, GLx) | Internally limited | Internally limited | A |
Gate drive pin sink current (GHx, GLx) | Internally limited | Internally limited | A |
Continuous low-side source sense pin voltage (SLx) | –1 | 1 | V |
Transient 200-ns low-side source sense pin voltage (SLx) | –5 | 5 | V |
Continuous shunt amplifier input pin voltage (SNx, SPx) | –1 | 1 | V |
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx) | –5 | 5 | V |
Reference input pin voltage (VREF) | –0.3 | 5.75 | V |
Shunt amplifier output pin voltage (SOx) | –0.3 | VVREF + 0.3 | V |
Ambient temperature, TA | –40 | 125 | °C |
Junction temperature, TJ | –40 | 150 | °C |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
GATE DRIVER | ||||
VVM | Gate driver power supply voltage (VM) | 9 | 75 | V |
VVDRAIN | Charge pump reference and drain voltage sense (VDRAIN) | 7 | 100 | V |
VI | Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) | 0 | 5.5 | V |
fPWM | Applied PWM signal (INHx, INLx) | 0 | 200(1) | kHz |
tSH | Switch-node slew rate range (SHx) | 0 | 2 | V/ns |
IGATE_HS | High-side average gate-drive current (GHx) | 0 | 25(1) | mA |
IGATE_LS | Low-side average gate-drive current (GLx) | 0 | 25(1) | mA |
IDVDD | External load current (DVDD) | 0 | 10(1) | mA |
VVREF | Reference voltage input (VREF) | 3 | 5.5 | V |
ISO | Shunt amplifier output current (SOx) | 0 | 5 | mA |
VOD | Open drain pullup voltage (nFAULT, SDO) | 0 | 5.5 | V |
IOD | Open drain output current (nFAULT, SDO) | 0 | 5 | mA |
TA | Operating ambient temperature | –40 | 125 | °C |
TJ | Operating junction temperature | –40 | 150 | °C |
THERMAL METRIC(1) | DRV8350F | DRV8353F | UNIT | |
---|---|---|---|---|
RTV (WQFN) | RTA (WQFN) | |||
32 PINS | 40 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 29.2 | 26.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 15.2 | 13.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 9.2 | 8.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 9.2 | 8.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.2 | 1.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLIES (DVDD, VCP, VGLS, VM) | |||||||
IVM | VM operating supply current | VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 8.5 | 13 | mA | ||
IVDRAIN | VDRAIN operating supply current | VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 1.9 | 4 | mA | ||
ISLEEP | Sleep mode supply current | ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C | 20 | 40 | µA | ||
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C | 100 | ||||||
tRST | Reset pulse time | ENABLE = 0 V period to reset faults | 5 | 40 | µs | ||
tWAKE | Turnon time | VVM > VUVLO, ENABLE = 3.3 V to outputs ready | 1 | ms | |||
tSLEEP | Turnoff time | ENABLE = 0 V to device sleep mode | 1 | ms | |||
VDVDD | DVDD regulator voltage | IDVDD = 0 to 10 mA | 4.75 | 5 | 5.25 | V | |
VVCP | VCP operating voltage with respect to VDRAIN |
VVM = 15 V, IVCP = 0 to 25 mA | 9 | 10.5 | 12 | V | |
VVM = 12 V, IVCP = 0 to 20 mA | 7.5 | 10 | 11.5 | ||||
VVM = 10 V, IVCP = 0 to 15 mA | 6 | 8 | 9.5 | ||||
VVM = 9 V, IVCP = 0 to 10 mA | 5.5 | 7.5 | 8.5 | ||||
VVGLS | VGLS operating voltage with respect to GND |
VVM = 15 V, IVGLS = 0 to 25 mA | 13 | 14.5 | 16 | V | |
VVM = 12 V, IVGLS = 0 to 20 mA | 10 | 11.5 | 12.5 | ||||
VVM = 10 V, IVGLS = 0 to 15 mA | 8 | 9.5 | 10.5 | ||||
VVM = 9 V, IVGLS = 0 to 10 mA | 7 | 8.5 | 9.5 | ||||
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI) | |||||||
VIL | Input logic low voltage | 0 | 0.8 | V | |||
VIH | Input logic high voltage | 1.5 | 5.5 | V | |||
VHYS | Input logic hysteresis | 100 | mV | ||||
IIL | Input logic low current | VVIN = 0 V | –5 | 5 | µA | ||
IIH | Input logic high current | VVIN = 5 V | 50 | 70 | µA | ||
RPD | Pulldown resistance | To GND | 100 | kΩ | |||
tPD | Propagation delay | INHx/INLx transition to GHx/GLx transition | 200 | ns | |||
FOUR-LEVEL H/W INPUTS (GAIN, MODE) | |||||||
VI1 | Input mode 1 voltage | Tied to GND | 0 | V | |||
VCOMP1 | Quad-level voltage comparator 1 | Voltage comparator between VI1 and VI2 | 1.156 | 1.256 | 1.356 | V | |
VI2 | Input mode 2 voltage | 47 kΩ ± 5% to tied GND | 1.9 | V | |||
VCOMP2 | Quad-level voltage comparator 1 | Voltage comparator between VI2 and VI3 | 2.408 | 2.508 | 2.608 | V | |
VI3 | Input mode 3 voltage | Hi-Z | 3.1 | V | |||
VCOMP3 | Quad-level voltage comparator 3 | Voltage comparator between VI3 and VI4 | 3.614 | 3.714 | 3.814 | V | |
VI4 | Input mode 4 voltage | Tied to DVDD | 5 | V | |||
RPU | Pullup resistance | Internal pullup to DVDD | 50 | kΩ | |||
RPD | Pulldown resistance | Internal pulldown to GND | 84 | kΩ | |||
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS) | |||||||
VI1 | Input mode 1 voltage | Tied to GND | 0 | V | |||
VCOMP1 | Seven-level voltage comparator 1 | Voltage comparator between VI1 and VI2 | 0.057 | 0.157 | 0.257 | V | |
VI2 | Input mode 2 voltage | 18 kΩ ± 5% tied to GND | 0.8 | V | |||
VCOMP2 | Seven-level voltage comparator 2 | Voltage comparator between VI2 and VI3 | 1.158 | 1.258 | 1.358 | V | |
VI3 | Input mode 3 voltage | 75 kΩ ± 5% tied to GND | 1.7 | V | |||
VCOMP3 | Seven-level voltage comparator 3 | Voltage comparator between VI3 and VI4 | 2.257 | 2.357 | 2.457 | V | |
VI4 | Input mode 4 voltage | Hi-Z | 2.5 | V | |||
VCOMP4 | Seven-level voltage comparator 4 | Voltage comparator between VI4 and VI5 | 2.561 | 2.661 | 2.761 | V | |
VI5 | Input mode 5 voltage | 75 kΩ ± 5% tied to DVDD | 3.3 | V | |||
VCOMP5 | Seven-level voltage comparator 5 | Voltage comparator between VI5 and VI6 | 3.615 | 3.715 | 3.815 | V | |
VI6 | Input mode 6 voltage | 18 kΩ ± 5% tied to DVDD | 4.2 | V | |||
VCOMP6 | Seven-level voltage comparator 6 | Voltage comparator between VI6 and VI7 | 4.75 | 4.85 | 4.95 | V | |
VI7 | Input mode 7 voltage | Tied to DVDD | 5 | V | |||
RPU | Pullup resistance | Internal pullup to DVDD | 73 | kΩ | |||
RPD | Pulldown resistance | Internal pulldown to GND | 73 | kΩ | |||
OPEN DRAIN OUTPUTS (nFAULT, SDO) | |||||||
VOL | Output logic low voltage | IO = 5 mA | 0.125 | V | |||
IOZ | Output high impedance leakage | VO = 5 V | –2 | 2 | µA | ||
GATE DRIVERS (GHx, GLx) | |||||||
VGSH | High-side gate drive voltage with respect to SHx |
VVM = 15 V, IVCP = 0 to 25 mA | 9 | 10.5 | 12 | V | |
VVM = 12 , IVCP = 0 to 20 mA | 7.5 | 10 | 11.5 | ||||
VVM = 10 V, IVCP = 0 to 15 mA | 6 | 8 | 9.5 | ||||
VVM = 9 V, IVCP = 0 to 10 mA | 5.5 | 7.5 | 8.5 | ||||
VGSL | Low-side gate drive voltage with respect to PGND |
VVM = 15 V, IVGLS = 0 to 25 mA | 9.5 | 11 | 12.5 | V | |
VVM = 12 V, IVGLS = 0 to 20 mA | 9 | 10.5 | 12 | ||||
VVM = 10 V, IVGLS = 0 to 15 mA | 7.5 | 9 | 10.5 | ||||
VVM = 9 V, IVGLS = 0 to 10 mA | 6.5 | 8 | 9.5 | ||||
tDEAD | Gate drive dead time |
SPI Device | DEAD_TIME = 00b | 50 | ns | ||
DEAD_TIME = 01b | 100 | ||||||
DEAD_TIME = 10b | 200 | ||||||
DEAD_TIME = 11b | 400 | ||||||
H/W Device | 100 | ||||||
tDRIVE | Peak current gate drive time |
SPI Device | TDRIVE = 00b | 500 | ns | ||
TDRIVE = 01b | 1000 | ||||||
TDRIVE = 10b | 2000 | ||||||
TDRIVE = 11b | 4000 | ||||||
H/W Device | 4000 | ||||||
IDRIVEP | Peak source gate current |
SPI Device | IDRIVEP_HS or IDRIVEP_LS = 0000b | 50 | mA | ||
IDRIVEP_HS or IDRIVEP_LS = 0001b | 50 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 0010b | 100 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 0011b | 150 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 0100b | 300 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 0101b | 350 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 0110b | 400 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 0111b | 450 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1000b | 550 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1001b | 600 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1010b | 650 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1011b | 700 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1100b | 850 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1101b | 900 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1110b | 950 | ||||||
IDRIVEP_HS or IDRIVEP_LS = 1111b | 1000 | ||||||
H/W Device | IDRIVE = Tied to GND | 50 | |||||
IDRIVE = 18 kΩ ± 5% tied to GND | 100 | ||||||
IDRIVE = 75 kΩ ± 5% tied to GND | 150 | ||||||
IDRIVE = Hi-Z | 300 | ||||||
IDRIVE = 75 kΩ ± 5% tied to DVDD | 450 | ||||||
IDRIVE = 18 kΩ ± 5% tied to DVDD | 700 | ||||||
IDRIVE = Tied to DVDD | 1000 | ||||||
IDRIVEN | Peak sink gate current |
SPI Device | IDRIVEN_HS or IDRIVEN_LS = 0000b | 100 | mA | ||
IDRIVEN_HS or IDRIVEN_LS = 0001b | 100 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 0010b | 200 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 0011b | 300 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 0100b | 600 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 0101b | 700 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 0110b | 800 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 0111b | 900 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1000b | 1100 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1001b | 1200 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1010b | 1300 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1011b | 1400 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1100b | 1700 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1101b | 1800 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1110b | 1900 | ||||||
IDRIVEN_HS or IDRIVEN_LS = 1111b | 2000 | ||||||
H/W Device | IDRIVE = Tied to GND | 100 | |||||
IDRIVE = 18 kΩ ± 5% tied to GND | 200 | ||||||
IDRIVE = 75 kΩ ± 5% tied to GND | 300 | ||||||
IDRIVE = Hi-Z | 600 | ||||||
IDRIVE = 75 kΩ ± 5% tied to DVDD | 900 | ||||||
IDRIVE = 18 kΩ ± 5% tied to DVDD | 1400 | ||||||
IDRIVE = Tied to DVDD | 2000 | ||||||
IHOLD | Gate holding current | Source current after tDRIVE | 50 | mA | |||
Sink current after tDRIVE | 100 | ||||||
ISTRONG | Gate strong pulldown current | GHx to SHx and GLx to SPx/SLx | 2 | A | |||
ROFF | Gate hold off resistor | GHx to SHx and GLx to SPx/SLx | 150 | kΩ | |||
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF) | |||||||
GCSA | Amplifier gain | SPI Device | CSA_GAIN = 00b | 4.85 | 5 | 5.15 | V/V |
CSA_GAIN = 01b | 9.7 | 10 | 10.3 | ||||
CSA_GAIN = 10b | 19.4 | 20 | 20.6 | ||||
CSA_GAIN = 11b | 38.8 | 40 | 41.2 | ||||
H/W Device | GAIN = Tied to GND | 4.85 | 5 | 5.15 | |||
GAIN = 47 kΩ ± 5% tied to GND | 9.7 | 10 | 10.3 | ||||
GAIN = Hi-Z | 19.4 | 20 | 20.6 | ||||
GAIN = Tied to DVDD | 38.8 | 40 | 41.2 | ||||
tSET | Settling time to ±1% | VO_STEP = 0.5 V, GCSA = 5 V/V | 250 | ns | |||
VO_STEP = 0.5 V, GCSA = 10 V/V | 500 | ||||||
VO_STEP = 0.5 V, GVSA = 20 V/V | 1000 | ||||||
VO_STEP = 0.5 V, GCSA = 40 V/V | 2000 | ||||||
VCOM | Common mode input range | –0.15 | 0.15 | V | |||
VDIFF | Differential mode input range | –0.3 | 0.3 | V | |||
VOFF | Input offset error | VSP = VSN = 0 V | –3 | 3 | mV | ||
VDRIFT | Drift offset | VSP = VSN = 0 V | 10 | µV/°C | |||
VLINEAR | SOx output voltage linear range | 0.25 | VVREF – 0.25 | V | |||
VBIAS | SOx output voltage bias | SPI Device | VSP = VSN = 0 V, VREF_DIV = 0b | VVREF – 0.3 | V | ||
VSP = VSN = 0 V, VREF_DIV = 1b | VVREF / 2 | ||||||
H/W Device | VSP = VSN = 0 V | VVREF / 2 | |||||
IBIAS | SPx/SNx input bias current | 250 | µA | ||||
VSLEW | SOx output slew rate | 60-pF load | 10 | V/µs | |||
IVREF | VREF input current | VVREF = 5 V | 1.5 | 2.5 | mA | ||
UGB | Unity gain bandwidth | DRV835xF: 60-pF load | 10 | MHz | |||
DRV835xFR: 60-pF load | 1 | MHz | |||||
PROTECTION CIRCUITS | |||||||
VVM_UV | VM undervoltage lockout | DRV835xF: VM falling, UVLO report | 8.0 | 8.3 | 8.8 | V | |
DRV835xF: VM rising, UVLO recovery | 8.2 | 8.5 | 9.0 | ||||
DRV835xFR: VM falling, UVLO report | 8.0 | 8.3 | 8.6 | ||||
DRV835xFR: VM rising, UVLO recovery | 8.2 | 8.5 | 8.8 | ||||
VVM_UVH | VM undervoltage hysteresis | Rising to falling threshold | 200 | mV | |||
tVM_UVD | VM undervoltage deglitch time | VM falling, UVLO report | 10 | µs | |||
VVDR_UV | VDRAIN undervoltage lockout | DRV835xF: VDRAIN falling, UVLO report | 6.1 | 6.4 | 6.8 | V | |
DRV835xF: VDRAIN rising, UVLO recovery | 6.3 | 6.6 | 7.0 | ||||
DRV835xFR: VDRAIN falling, UVLO report | 6.1 | 6.4 | 6.7 | ||||
DRV835xFR: VDRAIN rising, UVLO recovery | 6.3 | 6.6 | 6.9 | ||||
VVDR_UVH | VDRAIN undervoltage hysteresis | Rising to falling threshold | 200 | mV | |||
tVDR_UVD | VDRAIN undervoltage deglitch time | VDRAIN falling, UVLO report | 10 | µs | |||
VVCP_UV | VCP charge pump undervoltage lockout | VCP falling, GDUV report | VDRAIN + 5 | V | |||
VVGLS_UV | VGLS low-side regulator undervoltage lockout | VGLS falling, GDUV report | 4.25 | V | |||
VGS_CLAMP | High-side gate clamp | Positive clamping voltage | 12.5 | 13.5 | 16 | V | |
Negative clamping voltage | –0.7 | ||||||
VVDS_OCP | VDS overcurrent trip voltage |
SPI Device | DRV835xF: VDS_LVL = 0000b | 0.041 | 0.06 | 0.072 | V |
DRV835xF: VDS_LVL = 0001b | 0.051 | 0.07 | 0.084 | ||||
DRV835xF: VDS_LVL = 0010b | 0.061 | 0.08 | 0.096 | ||||
DRV835xF: VDS_LVL = 0011b | 0.071 | 0.09 | 0.108 | ||||
DRV835xF: VDS_LVL = 0100b | 0.081 | 0.1 | 0.115 | ||||
DRV835xFR: VDS_LVL = 0000b | 0.048 | 0.06 | 0.072 | ||||
DRV835xFR: VDS_LVL = 0001b | 0.056 | 0.07 | 0.084 | ||||
DRV835xFR: VDS_LVL = 0010b | 0.064 | 0.08 | 0.096 | ||||
DRV835xFR: VDS_LVL = 0011b | 0.072 | 0.09 | 0.108 | ||||
DRV835xFR: VDS_LVL = 0100b | 0.085 | 0.1 | 0.115 | ||||
VDS_LVL = 0101b | 0.18 | 0.2 | 0.22 | ||||
VDS_LVL = 0110b | 0.27 | 0.3 | 0.33 | ||||
VDS_LVL = 0111b | 0.36 | 0.4 | 0.44 | ||||
VDS_LVL = 1000b | 0.45 | 0.5 | 0.55 | ||||
VDS_LVL = 1001b | 0.54 | 0.6 | 0.66 | ||||
VDS_LVL = 1010b | 0.63 | 0.7 | 0.77 | ||||
VDS_LVL = 1011b | 0.72 | 0.8 | 0.88 | ||||
VDS_LVL = 1100b | 0.81 | 0.9 | 0.99 | ||||
VDS_LVL = 1101b | 0.9 | 1.0 | 1.1 | ||||
VDS_LVL = 1110b | 1.35 | 1.5 | 1.65 | ||||
VDS_LVL = 1111b | 1.8 | 2 | 2.2 | ||||
H/W Device | DRV835xF: VDS = Tied to GND | 0.041 | 0.06 | 0.072 | V | ||
DRV835xF: VDS = 18 kΩ ± 5% tied to GND | 0.081 | 0.1 | 0.115 | ||||
DRV835xFR: VDS = Tied to GND | 0.048 | 0.06 | 0.072 | ||||
DRV835xFR: VDS = 18 kΩ ± 5% tied to GND | 0.085 | 0.1 | 0.115 | ||||
VDS = 75 kΩ ± 5% tied to GND | 0.18 | 0.2 | 0.22 | ||||
VDS = Hi-Z | 0.36 | 0.4 | 0.44 | ||||
VDS = 75 kΩ ± 5% tied to DVDD | 0.63 | 0.7 | 0.77 | ||||
VDS = 18 kΩ ± 5% tied to DVDD | 0.9 | 1 | 1.1 | ||||
VDS = Tied to DVDD | Disabled | ||||||
tOCP_DEG | VDS and VSENSE overcurrent deglitch time | SPI Device | OCP_DEG = 00b | 1 | µs | ||
OCP_DEG = 01b | 2 | ||||||
OCP_DEG = 10b | 4 | ||||||
OCP_DEG = 11b | 8 | ||||||
H/W Device | 4 | ||||||
VSEN_OCP | VSENSE overcurrent trip voltage | SPI Device | SEN_LVL = 00b | 0.25 | V | ||
SEN_LVL = 01b | 0.5 | ||||||
SEN_LVL = 10b | 0.75 | ||||||
SEN_LVL = 11b | 1 | ||||||
H/W Device | 1 | ||||||
tRETRY | Overcurrent retry time | SPI Device | TRETRY = 0b | 8 | ms | ||
TRETRY = 1b | 50 | μs | |||||
H/W Device | 8 | ms | |||||
TOTW | Thermal warning temperature | Die temperature, TJ | 130 | 150 | 170 | °C | |
TOTSD | Thermal shutdown temperature | Die temperature, TJ | 150 | 170 | 190 | °C | |
THYS | Thermal hysteresis | Die temperature, TJ | 20 | °C |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tREADY | SPI ready after enable | VM > UVLO, ENABLE = 3.3 V | 1 | ms | ||
tCLK | SCLK minimum period | 100 | ns | |||
tCLKH | SCLK minimum high time | 50 | ns | |||
tCLKL | SCLK minimum low time | 50 | ns | |||
tSU_SDI | SDI input data setup time | 20 | ns | |||
tH_SDI | SDI input data hold time | 30 | ns | |||
tD_SDO | SDO output data delay time | SCLK high to SDO valid | 30 | ns | ||
tSU_nSCS | nSCS input setup time | 50 | ns | |||
tH_nSCS | nSCS input hold time | 50 | ns | |||
tHI_nSCS | nSCS minimum high time before active low | 400 | ns | |||
tDIS_nSCS | nSCS disable time | nSCS high to SDO high impedance | 10 | ns |
VVM = VVDRAIN |
IVM + IVDRAIN |
VVM = 48-V |
VVM = 15-V |
VVM = 12-V |
VVM = 9-V |
VVM = VVDRAIN |
IVM + IVDRAIN |
VVM = 48-V |
VVM = 15-V |
VVM = 12-V |
VVM = 9-V |
The DRV835xF family of devices are integrated 100-V gate drivers for three-phase motor drive applications. These devices decrease system component count, cost, and complexity by integrating three independent half-bridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages, and optional triple current shunt amplifiers. A standard serial peripheral interface (SPI) provides a simple method for configuring the various device settings and reading fault diagnostic information through an external controller. Alternatively, a hardware interface (H/W) option allows for configuring the most commonly used settings through fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage is generated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V. The low-side gate drive supply voltage is generated using a linear regulator from the VM power supply that regulates the VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate driver outputs. A smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive current strength allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the removal of external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture, VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent monitor reference.
The DRV8353F devices integrate three, bidirectional current-shunt amplifiers for monitoring the current level through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility to adjust the output bias point.
In addition to the high level of device integration, the DRV835xF family of devices provides a wide range of integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive undervoltage lockout (GDUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information available in the SPI registers on the SPI device version.
The DRV835xF family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN sizes are 5 × 5 mm for the 32-pin package and 6 × 6 mm for the 40-pin package.
The DRV835xF family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The VCP doubler charge pump provides the correct gate bias voltage to the high-side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support. The internal VGLS linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads.
The DRV835xF family of devices implement a smart gate-drive architecture which allows the user to dynamically adjust the gate drive current without requiring external gate current limiting resistors. Additionally, this architecture provides a variety of protection features for the external MOSFETs including automatic dead-time insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.
The DRV835xF family of devices provides four different PWM control modes to support various commutation and control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or PWM_MODE change.
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The corresponding INHx and INLx signals control the output state as listed in Table 8-1.
INLx | INHx | GLx | GHx | SHx |
---|---|---|---|---|
0 | 0 | L | L | Hi-Z |
0 | 1 | L | H | H |
1 | 0 | H | L | L |
1 | 1 | L | L | Hi-Z |
In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 8-2.
INLx | INHx | GLx | GHx | SHx |
---|---|---|---|---|
0 | X | L | L | Hi-Z |
1 | 0 | H | L | L |
1 | 1 | L | H | H |
In this mode, the DRV835xF family of devices uses 6-step block commutation tables that are stored internally. This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the direction of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the INHC pin low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this feature is not required.
LOGIC AND HALL INPUTS | GATE-DRIVE OUTPUTS | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STATE | INHC = 0 | INHC = 1 | PHASE A | PHASE B | PHASE C | DESCRIPTION | |||||||
INLA | INHB | INLB | INLA | INHB | INLB | GHA | GLA | GHB | GLB | GHC | GLC | ||
Stop | 0 | 0 | 0 | 0 | 0 | 0 | L | L | L | L | L | L | Stop |
Align | 1 | 1 | 1 | 1 | 1 | 1 | PWM | !PWM | L | H | L | H | Align |
1 | 1 | 1 | 0 | 0 | 0 | 1 | L | L | PWM | !PWM | L | H | B → C |
2 | 1 | 0 | 0 | 0 | 1 | 1 | PWM | !PWM | L | L | L | H | A → C |
3 | 1 | 0 | 1 | 0 | 1 | 0 | PWM | !PWM | L | H | L | L | A → B |
4 | 0 | 0 | 1 | 1 | 1 | 0 | L | L | L | H | PWM | !PWM | C → B |
5 | 0 | 1 | 1 | 1 | 0 | 0 | L | H | L | L | PWM | !PWM | C → A |
6 | 0 | 1 | 0 | 1 | 0 | 1 | L | H | PWM | !PWM | L | L | B → A |
LOGIC AND HALL INPUTS | GATE-DRIVE OUTPUTS | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STATE | INHC = 0 | INHC = 1 | PHASE A | PHASE B | PHASE C | DESCRIPTION | |||||||
INLA | INHB | INLB | INLA | INHB | INLB | GHA | GLA | GHB | GLB | GHC | GLC | ||
Stop | 0 | 0 | 0 | 0 | 0 | 0 | L | L | L | L | L | L | Stop |
Align | 1 | 1 | 1 | 1 | 1 | 1 | PWM | L | L | H | L | H | Align |
1 | 1 | 1 | 0 | 0 | 0 | 1 | L | L | PWM | L | L | H | B → C |
2 | 1 | 0 | 0 | 0 | 1 | 1 | PWM | L | L | L | L | H | A → C |
3 | 1 | 0 | 1 | 0 | 1 | 0 | PWM | L | L | H | L | L | A → B |
4 | 0 | 0 | 1 | 1 | 1 | 0 | L | L | L | H | PWM | L | C → B |
5 | 0 | 1 | 1 | 1 | 0 | 0 | L | H | L | L | PWM | L | C → A |
6 | 0 | 1 | 0 | 1 | 0 | 1 | L | H | PWM | L | L | L | B → A |
Figure 8-5 and Figure 8-6 show the different possible configurations in 1x PWM mode.
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This control mode allows for the external controller to bypass the internal dead-time handshake of the DRV835xF or to utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge. These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches. In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side and low-side MOSFETs are turned on at the same time.
INLx | INHx | GLx | GHx |
---|---|---|---|
0 | 0 | L | L |
0 | 1 | L | H |
1 | 0 | H | L |
1 | 1 | H | H |
Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using both of the monitors is not possible if both the high-side and low-side gate drivers are being operated independently.
In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in Figure 8-7.
If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors is still possible. Connect the SHx pin as shown in Figure 8-8 or Figure 8-9. The unused gate driver and the corresponding input can be left disconnected.
The DRV835xF family of devices support two different interface modes (SPI and hardware) to allow the end application to design for either flexibility or simplicity. The two interface modes share the same four pins, allowing the different versions to be pin to pin compatible. This allows for application designers to evaluate with one interface version and potentially switch to another with minimal modifications to their design.
The SPI devices support a serial communication bus that allows for an external controller to send and receive data with the DRV835xF. This allows for the external controller to configure device settings and read detailed fault information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.
For more information on the SPI, see the Section 8.5.1 section.
Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE, MODE, and VDS. This allows for the application designer to configure the most commonly used device settings by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT pin.
For more information on the hardware interface, see the Section 8.3.3 section.
The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep a fixed output voltage of VVDRAIN + 10.5 V and supports an average output current of 25 mA. When VVM is less than 12 V, the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V with respect to VVDRAIN when unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven MOSFET conditions.
The charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VDRAIN and VCP pins to act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required between the CPH and CPL pins to act as the flying capacitor.
The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.
Since the charge pump output is regulated to VVDRAIN + 10.5 V this allows for VM to be supplied either directly from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an externally available power supply. Figure 8-13 and Figure 8-14 show examples of the DRV835xF configured in either single supply or dual supply configuration.
The DRV835xF gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE which are detailed in the Section 8.3.1.4.1 section and Section 8.3.1.4.2 section. Figure 8-15 shows the high-level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters of the external power MOSFET used in the system and the desired rise and fall times (see the Section 9 section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from overvoltage conditions in the case of external short-circuit events on the MOSFET.
The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates. The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of diode recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to parasitics in the external half-bridge. IDRIVE operates on the principal that the MOSFET VDS slew rates are predominately determined by the rate of gate charge (or gate current) delivered during the MOSFET QGD or Miller charging region. By allowing the gate driver to adjust the gate current, it can effectively control the slew rate of the external power MOSFETs.
IDRIVE allows the DRV835xF family of devices to dynamically switch between gate drive currents either through a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices provide 16 IDRIVE settings ranging between 50-mA to 1-A source and 100-mA to 2-A sink. Hardware interface devices provides 7 IDRIVE settings between the same ranges. The gate drive current setting is delivered to the gate during the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET turnon or turnoff, the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficiency. Additional details on the IDRIVE settings are described in the Section 8.6 section for the SPI devices and in the Section 8.3.3 section for the hardware interface devices.
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross conduct and cause shoot-through. The DRV835xF family of devices use VGS voltage monitors to measure the MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time value. This feature allows the gate-driver dead time to adjust for variation in the system such a temperature drift and variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is adjustable through the registers on SPI devices.
The automatic dead-time insertion has a limitation when the gate driver is transitioning from high-side MOSFET on to low-side MOSFET on when the phase current is coming into the external half-bridge. In this case, the high-side diode will conduct during the dead-time and hold up the switch-node voltage to VDRAIN. In this case, an additional delay of approximately 100-200 ns is introduced into the dead-time handshake. This is introduced due to the need to discharge the voltage present on the internal VGS detection circuit.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state machine enables a strong pulldown ISTRONG current on the opposite MOSFET gate whenever a MOSFET is switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a pair of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If at the end of the tDRIVE period the VGS voltage has not reached the correct threshold the gate driver will report a fault. To make sure that a false fault is not detected, a tDRIVE time should be selected that is longer than the time required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and will terminate if another PWM command is received while active. Additional details on the TDRIVE settings are described in the Section 8.6 section for SPI devices and in the Section 8.3.3 section for hardware interface devices.
Figure 8-16 shows an example of the TDRIVE state machine in operation.
The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay, and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to the overall propagation delay of the device.
The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three current-shunt amplifiers (DRV8353F), the low-side VDS monitors measure the voltage between the SHx and SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the external half-bridges. On device options without the current shunt amplifiers (DRV8350F) the low-side VDS monitor measures between the SHx and SLx pins.
For the SPI devices, the low-side VDS monitor reference point can be changed between the SPx and SNx pins if desired with the LS_REF register setting. This is only for the low-side VDS monitor. The high-side VDS monitor stays between the VDRAIN and SHx pins.
The VVDS_OCP threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V on hardware interface devices. Additional information on the VDS monitor levels are described in the Section 8.6 section for SPI devices and in the Section 8.3.3 section hardware interface device.
The DRV835xF family of devices provides a separate sense and reference pin for the common point of the high-side MOSFET drain. This pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors (VDRAIN) and the power supply (VM) to stay separate and prevent noise on the VDRAIN sense line.
The VDRAIN pin serves as the reference point for the integrated charge pump. This makes sure that the charge pump reference stays with respect to the power MOSFET supply through voltage transient conditions.
Since the charge pump is referenced to VDRAIN, this also allows for VM to supplied either directed from the power MOSFET supply (VDRAIN) or from an independent supply. This allows for a configuration where VM can be supplied from an efficient low voltage supply to increase the device efficiency.
A 5-V, 10-mA linear regulator is integrated into the DRV835xF family of devices and is available for use by external circuitry. This regulator can provide the supply voltage for low-current supporting circuitry. The output of the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor routed directly back to the adjacent DGND or GND ground pin.
The DVDD nominal, no-load output voltage is 5 V. When the DVDD load current exceeds 10 mA, the regulator functions like a constant-current source. The output voltage drops significantly with a current load greater than 10 mA.
Use Equation 1 to calculate the power dissipated in the device because of the DVDD linear regulator.
For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in Equation 2.
Figure 8-20 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.
Figure 8-21 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices. The input can be set with an external resistor.
Figure 8-22 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices. The input can be set with an external resistor.
Figure 8-23 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output requires an external pullup resistor to function correctly.