SLVSGH7C November 2022 – May 2024 DRV8410
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
An analog current limit circuit on each FET limits the current through the FET by limiting the gate drive internally. If this current limit persists for longer than the OCP deglitch time (tOCP), all FETs in the H-bridge will disable and the nFAULT pin will assert low. The driver re-enables after the OCP retry period (tRETRY) has passed. nFAULT becomes high again at this time and normal operation resumes. If the fault condition is still present, the cycle repeats as shown in Figure 8-6. Please note that only the H-bridge where an overcurrent condition is detected will be disabled while the other bridge will function normally.
Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short to ground, supply, or across the motor winding will all result in an overcurrent shutdown. The xISEN pins also integrate a separate overcurrent trip threshold specified by VOCP_ISEN for additional protection when the VM voltage is low or the RSENSE resistance on the xISEN pin is high.