SLVSHA4 June 2024 DRV8421
PRODUCTION DATA
The DRV8421A is active until power is switched off. The DRV8421B is active until power is switched off or unless the EN pin is brought logic low which forces the device into sleep mode. In sleep mode, the H-bridge FETs are disabled Hi-Z. Note that tSLEEP must elapse EN pin before the device goes to sleep mode. The DRV8421B is brought out of sleep mode automatically if EN pin is brought logic high. Note that tWAKE must elapse before the output change state after wake-up.
When VVM falls below the VM UVLO threshold (VUVLO), the output driver and internal logic are reset.
MODE | CONDITION | H-BRIDGE | VINT |
---|---|---|---|
Operating | 4 V < VVM < 18 V nSLEEP pin = 1 | Operating | Operating |
Sleep | 4 V < VVM < 18 V EN pin = 0 | Disabled | Disabled |
Fault | Any fault condition met | Disabled | Depends on fault |