SLVSHA4 June   2024 DRV8421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 PWM Motor Drivers
      2. 7.3.2 Truth Tables
      3. 7.3.3 Parallel Operation
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 OCP
        2. 7.3.4.2 TSD
        3. 7.3.4.3 UVLO
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance Sizing
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Community Resources
    2. 9.2 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM)
VVM VM operating voltage 4 18 V
IVM VM operating supply current VVM = 12 V, excluding winding current 1.2 1.35 1.5 mA
IVMQ VM sleep mode supply current (2-wire input only) VVM = 12V, EN = 0 (2-wire input only) 0.5 1.2 3 μA
tSLEEP Sleep time (2-wire input only) EN = 1 to sleep mode (2-wire input only) 1 ms
tWAKE Wake time (2-wire input only) EN = 0 to output transition (2-wire input only) 1 ms
tON Power-on time VVM > VUVLO rising to output transition 1 ms
LOGIC-LEVEL INPUTS (IN1, IN2, IN3, IN4, EN)
VIL Input logic low voltage 0 0.7 V
VIH Input logic high voltage 1.6 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VI = 0 V -1 1 µA
IIH Input logic high current VI = 5 V 1 30 µA
RPD Pulldown resistance (2-wire input version) IN1 200 kΩ
IN2 170 kΩ
RPD Pulldown resistance (4-wire input version) IN1/IN2 200 kΩ
IN3/IN4 170 kΩ
RPD Pulldown resistance EN (2-wire input only) 500 kΩ
tDEG Input deglitch time INx 200 ns
tPROP Propagation delay INx edge to output change 400 ns
CONTROL OUTPUTS (NFAULT)
VOL Output logic low voltage IO = 5 mA 0.5 V
IOH Output logic high leakage VO = 3.3 V -1 1 µA
MOTOR DRIVER OUTPUTS (OUT1, OUT2, OUT3, OUT4)
RDS(ON) High-side FET on resistance VVM = 12 V, IO = 0.5 A, TJ = 25°C 550 mΩ
RDS(ON) High-side FET on resistance VVM = 12 V, IO = 0.5 A, TJ = 85°C(1) 660 mΩ
RDS(ON) Low-side FET on resistance VVM = 12 V, IO = 0.5 A, TJ = 25°C 350 mΩ
RDS(ON) Low-side FET on resistance VVM = 12 V, IO = 0.5 A, TJ = 85°C(1) 420 mΩ
IOFF Off-state leakage current VVM = 5 V, TJ = 25°C (2-wire input only) -1 1 μA
tRISE Output rise time 60 ns
tFALL Output fall time 60 ns
tDEAD Output dead time Internal dead time 200 ns
PROTECTION CIRCUITS
VUVLO VM undervoltage lockout VVM falling; UVLO report 2.9 V
VVM rising; UVLO recovery 3 V
IOCP Overcurrent protection trip level 2 A
tDEG Overcurrent deglitch time 2.8 µs
tOCP Overcurrent protection period 1.6 ms
TTSD(1) Thermal shutdown temperature Die temperature TJ 150 160 180 °C
THYS(1) Thermal shutdown hysteresis Die temperature TJ 35 °C
(1) Not tested in production; limits are based on characterization data