Pin to pin compatible with -
The DRV8424/25 are stepper motor drivers for industrial and consumer applications. The device is fully integrated with two N-channel power MOSFET H-bridge drivers, a microstepping indexer, and integrated current sensing. The DRV8424 is capable of driving up to 2.5-A full-scale output current; and the DRV8425 is capable of driving up to 2-A full-scale output current (dependent on PCB design).
The DRV8424/25 use an internal current sense architecture to eliminate the need for two external power sense resistors, saving PCB area and system cost. The devices use an internal PWM current regulation scheme selectable between smart tune, slow and mixed decay options. Smart tune automatically adjusts for optimal current regulation, compensates for motor variation and aging effects and reduces audible noise from the motor.
A simple STEP/DIR interface allows an external controller to manage the direction and step rate of the stepper motor. The device can be configured in full-step to 1/256 microstepping. A low-power sleep mode is provided using a dedicated nSLEEP pin. Protection features are provided for supply undervoltage, charge pump faults, overcurrent, short circuits, and overtemperature. Fault conditions are indicated by the nFAULT pin.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8424PWPR | HTSSOP (28) | 9.7mm x 4.4mm |
DRV8424RGER | VQFN (24) | 4.0mm x 4.0mm |
DRV8425PWPR | HTSSOP (28) | 9.7mm x 4.4mm |
DRV8425RGER | VQFN (24) | 4.0mm x 4.0mm |
Changes from Revision B (May 2021) to Revision C (July 2022)
Changes from Revision A (October 2020) to Revision B (May 2021)
Changes from Revision * (May 2020) to Revision A (October 2020)
PART NUMBER | RDS(ON) (HS + LS) (mΩ) | Full-Scale Current Per Bridge (A) |
---|---|---|
DRV8424 | 330 | 2.5 |
DRV8425 | 550 | 2 |
PIN | I/O | TYPE | DESCRIPTION | ||
---|---|---|---|---|---|
NAME | NO. | ||||
HTSSOP | VQFN | ||||
AOUT1 | 4, 5 | 3 | O | Output | Winding A output. Connect to stepper motor winding. |
AOUT2 | 6, 7 | 4 | O | Output | Winding A output. Connect to stepper motor winding. |
PGND | 3, 12 | 2, 7 | — | Power | Power ground. Connect to system ground. |
BOUT2 | 8, 9 | 5 | O | Output | Winding B output. Connect to stepper motor winding |
BOUT1 | 10, 11 | 6 | O | Output | Winding B output. Connect to stepper motor winding |
CPH | 28 | 23 | — | Power | Charge pump switching node. Connect a X7R, 0.022-µF, VM-rated ceramic capacitor from CPH to CPL. |
CPL | 27 | 22 | |||
DIR | 24 | 19 | I | Input | Direction input. Logic level sets the direction of stepping; internal pulldown resistor. |
ENABLE | 25 | 20 | I | Input | Logic low to disable device outputs; logic high to enable; internal pullup to DVDD. Also determines the type of OCP and OTSD response. |
DVDD | 15 | 10 | O | Power | Logic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND. |
GND | 14 | 9 | — | Power | Device ground. Connect to system ground. |
VREF | 17 | 12 | I | Input | Current set reference input. Maximum value 3.3 V for DRV8424 and 2.64V for DRV8425. DVDD can be used to provide VREF through a resistor divider. |
M0 | 18 | 13 | I | Input | Microstepping mode-setting pins. Sets the step mode; internal pulldown resistor. |
M1 | 22 | 17 | |||
DECAY0 | 21 | 16 | I | Input | Decay-mode setting pins. Sets the decay mode (see the Section 7.3.6 section). |
DECAY1 | 20 | 15 | |||
STEP | 23 | 18 | I | Input | Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor. |
VCP | 1 | 24 | — | Power | Charge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM. |
VM | 2, 13 | 1, 8 | — | Power | Power supply. Connect to motor supply voltage and bypass to PGND with two 0.01-µF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM. |
TOFF | 19 | 14 | I | Input | Sets the Decay mode off time during current chopping; four level pin. Also sets the ripple current in smart tune ripple control mode. |
nFAULT | 16 | 11 | O | Open Drain | Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor. |
nSLEEP | 26 | 21 | I | Input | Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. An nSLEEP low pulse clears faults. |
PAD | - | - | - | - | Thermal pad. Connect to system ground. |