SLOSE59C May   2020  – July 2022 DRV8424 , DRV8425

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mixed Decay for Increasing and Decreasing Current
        4. 7.3.6.4 Smart tune Dynamic Decay
        5. 7.3.6.5 Smart tune Ripple Control
        6. 7.3.6.6 PWM OFF Time
        7. 7.3.6.7 Blanking time
      7. 7.3.7  Charge Pump
      8. 7.3.8  Linear Voltage Regulators
      9. 7.3.9  Logic Level, tri-level and quad-level Pin Diagrams
      10. 7.3.10 nFAULT Pin
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.11.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.11.3 Overcurrent Protection (OCP)
          1. 7.3.11.3.1 Latched Shutdown
          2. 7.3.11.3.2 Automatic Retry
        4. 7.3.11.4 Thermal Shutdown (OTSD)
          1. 7.3.11.4.1 Latched Shutdown
          2. 7.3.11.4.2 Automatic Retry
        5. 7.3.11.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      3. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      4. 7.4.4 nSLEEP Reset Pulse
      5. 7.4.5 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
          1. 8.2.4.1.1 Conduction Loss
          2. 8.2.4.1.2 Switching Loss
          3. 8.2.4.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.4.1.4 Total Power Dissipation
        2. 8.2.4.2 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-9F2C70F8-DF97-411C-B02D-DD9AAD9AC7CC-low.gifFigure 5-1 PWP PowerPAD™ Package28-Pin HTSSOPTop View
GUID-AD87F220-FFFB-408E-A557-76DE0B20D2C4-low.gifFigure 5-2 RGE Package24-Pin VQFN with Exposed Thermal PADTop View
Table 5-1 Pin Functions
PIN I/O TYPE DESCRIPTION
NAME NO.
HTSSOP VQFN
AOUT1 4, 5 3 O Output Winding A output. Connect to stepper motor winding.
AOUT2 6, 7 4 O Output Winding A output. Connect to stepper motor winding.
PGND 3, 12 2, 7 — Power Power ground. Connect to system ground.
BOUT2 8, 9 5 O Output Winding B output. Connect to stepper motor winding
BOUT1 10, 11 6 O Output Winding B output. Connect to stepper motor winding
CPH 28 23 — Power Charge pump switching node. Connect a X7R, 0.022-µF, VM-rated ceramic capacitor from CPH to CPL.
CPL 27 22
DIR 24 19 I Input Direction input. Logic level sets the direction of stepping; internal pulldown resistor.
ENABLE 25 20 I Input Logic low to disable device outputs; logic high to enable; internal pullup to DVDD. Also determines the type of OCP and OTSD response.
DVDD 15 10 O Power Logic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
GND 14 9 — Power Device ground. Connect to system ground.
VREF 17 12 I Input Current set reference input. Maximum value 3.3 V for DRV8424 and 2.64V for DRV8425. DVDD can be used to provide VREF through a resistor divider.
M0 18 13 I Input Microstepping mode-setting pins. Sets the step mode; internal pulldown resistor.
M1 22 17
DECAY0 21 16 I Input Decay-mode setting pins. Sets the decay mode (see the Section 7.3.6 section).
DECAY1 20 15
STEP 23 18 I Input Step input. A rising edge causes the indexer to advance one step; internal pulldown resistor.
VCP 1 24 — Power Charge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM.
VM 2, 13 1, 8 — Power Power supply. Connect to motor supply voltage and bypass to PGND with two 0.01-µF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM.
TOFF 19 14 I Input Sets the Decay mode off time during current chopping; four level pin. Also sets the ripple current in smart tune ripple control mode.
nFAULT 16 11 O Open Drain Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP 26 21 I Input Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. An nSLEEP low pulse clears faults.
PAD - - - - Thermal pad. Connect to system ground.