SLOSE54C June   2020  – July 2022 DRV8428

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2 PWM Motor Drivers
      3. 7.3.3 Microstepping Indexer
      4. 7.3.4 Controlling VREF with an MCU DAC
      5. 7.3.5 Current Regulation, Off-time and Decay Modes
        1. 7.3.5.1 Mixed Decay
        2. 7.3.5.2 Smart tune Dynamic Decay
        3. 7.3.5.3 Smart tune Ripple Control
        4. 7.3.5.4 Blanking time
      6. 7.3.6 Linear Voltage Regulators
      7. 7.3.7 Logic Level, tri-level, quad-level and seven-level Pin Diagrams
        1. 7.3.7.1 EN/nFAULT Pin
      8. 7.3.8 Protection Circuits
        1. 7.3.8.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.8.2 Overcurrent Protection (OCP)
        3. 7.3.8.3 Thermal Shutdown (OTSD)
        4. 7.3.8.4 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Disable Mode (nSLEEP = 1, EN/nFAULT = 0/Hi-Z)
      3. 7.4.3 Operating Mode (nSLEEP = 1, EN/nFAULT = 1)
      4. 7.4.4 Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
        4. 8.2.2.4 Application Curves
      3. 8.2.3 Thermal Application
        1. 8.2.3.1 Power Dissipation
          1. 8.2.3.1.1 Conduction Loss
          2. 8.2.3.1.2 Switching Loss
          3. 8.2.3.1.3 Power Dissipation Due to Quiescent Current
          4. 8.2.3.1.4 Total Power Dissipation
        2. 8.2.3.2 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Current Regulation, Off-time and Decay Modes

During PWM current chopping, the H-bridge is enabled to drive through the motor winding until the PWM current chopping threshold is reached. This is shown in Figure 7-6, Item 1.

The current through the motor windings is regulated by an adjustable, off-time PWM current-regulation circuit. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage, inductance of the winding, and the magnitude of the back EMF present. When the current hits the current regulation threshold, the bridge enters a decay mode for a period of time determined by the seven-level DECAY/TOFF pin setting to decrease the current. After the off-time expires, the bridge is re-enabled, starting another PWM cycle.

GUID-8A90DE6A-52D4-4064-8A0C-02DDCDE7EE70-low.gifFigure 7-5 Current Chopping Waveform

Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or slow decay. In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to allow winding current to flow in a reverse direction. Fast decay mode is shown in Figure 7-6, item 2. In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is shown in Figure 7-6, Item 3.

The PWM chopping current is set by a comparator which monitors the voltage across the current sense MOSFETs in parallel with the low-side power MOSFETs. The current sense MOSFETs are biased with a reference current that is the output of a current-mode sine-weighted DAC whose full-scale reference current is set by the voltage at the VREF pin.

The chopping current (IFS) can be calculated as IFS (A) = VREF (V) / KV (V/A) = VREF (V) / 3 (V/A).

GUID-18AEE5D7-6CD1-4C1D-ABFA-643A18D2A4EB-low.gifFigure 7-6 Decay Modes

The decay mode and off time for each bridge is selected by setting the seven-level DECAY/TOFF pin as shown in Table 7-6.

Table 7-6 Decay Mode Settings
DECAY/TOFFDECAY MODEOFF TIME
0Smart tune Ripple Control-
14.7 kΩ to GNDMixed 30% Decay7 µs
44.2 kΩ to GND16 µs
100 kΩ to GND32 µs
249 kΩ to GNDSmart tune Dynamic Decay7 µs
Hi-Z16 µs
DVDD32 µs