SLOSE47A November   2020  – May 2022 DRV8434

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
      1. 6.6.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2  PWM Motor Drivers
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Controlling VREF with an MCU DAC
      5. 7.3.5  Current Regulation
      6. 7.3.6  Decay Modes
        1. 7.3.6.1 Slow Decay for Increasing and Decreasing Current
        2. 7.3.6.2 Slow Decay for Increasing Current, Mixed Decay for Decreasing Current
        3. 7.3.6.3 Mixed Decay for Increasing and Decreasing Current
        4. 7.3.6.4 Smart tune Dynamic Decay
        5. 7.3.6.5 Smart tune Ripple Control
        6. 7.3.6.6 PWM OFF Time
        7. 7.3.6.7 Blanking time
      7. 7.3.7  Charge Pump
      8. 7.3.8  Linear Voltage Regulators
      9. 7.3.9  Logic Level, Tri-Level and Quad-Level Pin Diagrams
        1. 7.3.9.1 nFAULT Pin
      10. 7.3.10 Protection Circuits
        1. 7.3.10.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.10.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.10.3 Overcurrent Protection (OCP)
          1. 7.3.10.3.1 Latched Shutdown
          2. 7.3.10.3.2 Automatic Retry
        4. 7.3.10.4 Open-Load Detection (OL)
        5. 7.3.10.5 Thermal Shutdown (OTSD)
          1. 7.3.10.5.1 Latched Shutdown
          2. 7.3.10.5.2 Automatic Retry
        6.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2.      52
      3. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      4. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      5. 7.4.4 nSLEEP Reset Pulse
      6.      Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Mode
        4. 8.2.2.4 Application Curves
        5. 8.2.2.5 Thermal Application
          1. 8.2.2.5.1 Power Dissipation
          2. 8.2.2.5.2 Conduction Loss
          3. 8.2.2.5.3 Switching Loss
          4. 8.2.2.5.4 Power Dissipation Due to Quiescent Current
          5. 8.2.2.5.5 Total Power Dissipation
          6. 8.2.2.5.6 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9 Logic Level, Tri-Level and Quad-Level Pin Diagrams

Figure 7-15 shows the input structure for M0, DECAY0 and ENABLE pins.

GUID-20D93CF1-F368-41C3-9DAE-FEB1479CD244-low.jpgFigure 7-15 Tri-Level Input Pin Diagram

Figure 7-16 shows the input structure for DECAY1 pin.

GUID-DDE798A7-F33E-44EE-BB8B-6440B8359002-low.jpgFigure 7-16 DECAY1 Pin Diagram

Figure 7-17 shows the input structure for M1 and TOFF pins.

GUID-6E92209A-F941-42CA-9588-31BB0E24D877-low.jpgFigure 7-17 Quad-Level Input Pin Diagram

Figure 7-18 shows the input structure for STEP, DIR and nSLEEP pins.

GUID-ACA3E2E2-B31F-46C5-970A-181128FDF3EC-low.gifFigure 7-18 Logic-Level Input Pin Diagram