SLOSE48 December   2020 DRV8434A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Indexer Timing Requirements
      1. 6.6.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Stepper Motor Driver Current Ratings
        1. 7.3.1.1 Peak Current Rating
        2. 7.3.1.2 RMS Current Rating
        3. 7.3.1.3 Full-Scale Current Rating
      2. 7.3.2 PWM Motor Drivers
      3. 7.3.3 Microstepping Indexer
      4. 7.3.4 Controlling VREF with an MCU DAC
      5. 7.3.5 Current Regulation and Decay Mode
        1. 7.3.5.1 Smart tune Ripple Control
        2. 7.3.5.2 Blanking Time
      6. 7.3.6 Charge Pump
      7. 7.3.7 Linear Voltage Regulators
      8. 7.3.8 Logic Level, tri-level and quad-level Pin Diagrams
        1. 7.3.8.1 nFAULT Pin
      9. 7.3.9 Protection Circuits
        1. 7.3.9.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.9.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.9.3 Overcurrent Protection (OCP)
        4. 7.3.9.4 Stall Detection
        5. 7.3.9.5 Open-Load Detection (OL)
        6. 7.3.9.6 Thermal Shutdown (OTSD)
        7.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2.      43
      3. 7.4.2 Disable Mode (nSLEEP = 1, ENABLE = 0)
      4. 7.4.3 Operating Mode (nSLEEP = 1, ENABLE = Hi-Z/1)
      5. 7.4.4 nSLEEP Reset Pulse
      6.      Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Mode
        4. 8.2.2.4 Application Curves
        5. 8.2.2.5 Thermal Application
          1. 8.2.2.5.1 Power Dissipation
          2. 8.2.2.5.2 Conduction Loss
          3. 8.2.2.5.3 Switching Loss
          4. 8.2.2.5.4 Power Dissipation Due to Quiescent Current
          5. 8.2.2.5.5 Total Power Dissipation
          6. 8.2.2.5.6 Device Junction Temperature Estimation
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, DVDD)
IVM VM operating supply current ENABLE = 1, nSLEEP = 1, No motor load 5 6.5 mA
IVMQ VM sleep mode supply current nSLEEP = 0 2 4 μA
tSLEEP Sleep time nSLEEP = 0 to sleep-mode

120

 μs
tRESET nSLEEP reset pulse nSLEEP low to clear fault

20

40

 μs
tWAKE Wake-up time nSLEEP = 1 to output transition 0.8 1.2 ms
tON Turn-on time VM > UVLO to output transition 0.8 1.2 ms

tEN

Enable time

ENABLE = 0/1 to output transition

5

 μs
VDVDD Internal regulator voltage No external load, 6V < VVM < 48V 4.75 5 5.25 V
No external load, VVM = 4.5V

4.2

4.35

V
CHARGE PUMP (VCP, CPH, CPL)
VVCP VCP operating voltage 6V < VVM < 48V VVM + 5 V
f(VCP) Charge pump switching frequency VVM > UVLO; nSLEEP = 1 360 kHz
LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP)
VIL Input logic-low voltage 0 0.6 V
VIH Input logic-high voltage 1.5 5.5 V
VHYS Input logic hysteresis 150 mV
IIL Input logic-low current VIN = 0 V –1 1 μA
IIH Input logic-high current VIN = 5 V 100 μA
TRI-LEVEL INPUTS (M0, ENABLE)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 Input Hi-Z voltage Hi-Z 1.8 2 2.2 V
VI3 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IO Output pull-up current 10 μA
QUAD-LEVEL INPUT (M1, STL_MODE)
VI1 Input logic-low voltage Tied to GND 0 0.6 V
VI2 330kΩ ± 5% to GND 1 1.25 1.4 V
VI3 Input Hi-Z voltage Hi-Z 1.8 2 2.2 V
VI4 Input logic-high voltage Tied to DVDD 2.7 5.5 V
IIL Output pull-up current 10 μA
TORQUE COUNT INPUT/ STALL THRESHOLD OUTPUT (TRQ_CNT/STL_TH)
VO1 Output low voltage STL_MODE = 0V 0.1 V
VO2 Output High voltage STL_MODE = 0V 2.4 V
VI1 Input low voltage STL_MODE = DVDD 0.1 V
VI2 Input High voltage STL_MODE = DVDD 2.4 V
NBIT Torque-count DAC Resolution 12 Bits
CLOAD TRQ_CNT/STL_TH pin Capacitive Load RLOAD = Infinite, Phase margin = 45° 1 nF
ISHORT TRQ_CNT/STL_TH pin short-circuit current Full scale output shorted to GND 2 mA
tS DAC Output voltage settling time 99% of final target 50 μs
CONTROL OUTPUTS (nFAULT, STL_REP)
VOL Output logic-low voltage IO = 5 mA 0.5 V
IOH Output logic-high leakage –1 1 μA
VIL Input logic-low voltage STL_REP, pulled low to disable stall reporting 0 0.6 V
VIH Input logic-high voltage STL_REP, pulled high to enable stall reporting 1.5 5.5 V
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2)
RDS(ON) High-side FET on resistance TJ = 25 °C, IO = -1 A 165 200 mΩ
TJ = 125 °C, IO = -1 A 250 300 mΩ
TJ = 150 °C, IO = -1 A 280 350 mΩ
RDS(ON) Low-side FET on resistance TJ = 25 °C, IO = 1 A 165 200 mΩ
TJ = 125 °C, IO = 1 A 250 300 mΩ
TJ = 150 °C, IO = 1 A 280 350 mΩ
tSR Output slew rate VVM = 24 V, IO = 1 A, Between 10% and 90% 240 V/µs
PWM CURRENT CONTROL (VREF)
KV Transimpedance gain

VREF = 3.3 V

 1.254 1.32 1.386 V/A

IVREF

VREF Leakage Current

 VREF = 3.3 V

8.25

 μA
ΔITRIP Current trip accuracy 0.25 A < IO < 0.5 A –12 12 %
0.5 A < IO < 1 A –6

6
1 A < IO < 2.5 A –4

4
IO,CH AOUT and BOUT current matching IO = 2.5 A –2.5 2.5 %
PROTECTION CIRCUITS
VUVLO VM UVLO lockout VM falling, UVLO falling 4.1 4.25 4.35 V
VM rising, UVLO rising 4.2 4.35 4.45
VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 100 mV
VCPUV Charge pump undervoltage VCP falling; CPUV report VVM + 2 V
IOCP Overcurrent protection Current through any FET 4 A
tOCP Overcurrent deglitch time 2 μs
tRETRY Overcurrent retry time 4 ms
tOL Open load detection time 50 ms
IOL Open load current threshold 75 mA
TOTSD Thermal shutdown Die temperature TJ 150 165 180 °C
THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 20 °C