SLOSE49 November   2020 DRV8434E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
      2. 7.3.2 Current Regulation
      3. 7.3.3 Decay Modes
        1. 7.3.3.1 Mixed Decay
        2. 7.3.3.2 Fast Decay
        3. 7.3.3.3 Smart tune Dynamic Decay
        4. 7.3.3.4 Smart tune Ripple Control
        5. 7.3.3.5 Blanking time
      4. 7.3.4 Charge Pump
      5. 7.3.5 Linear Voltage Regulators
      6. 7.3.6 Logic and Quad-Level Pin Diagrams
        1. 7.3.6.1 nFAULT Pin
      7. 7.3.7 Protection Circuits
        1. 7.3.7.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.7.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.7.3 Overcurrent Protection (OCP)
        4. 7.3.7.4 Thermal Shutdown (OTSD)
        5.       Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4.      Functional Modes Summary
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Current Regulation
        2. 8.2.2.2 Power Dissipation and Thermal Calculation
      3. 8.2.3 Application Curves
    3. 8.3 Alternate Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
        1. 8.3.2.1 Current Regulation
        2. 8.3.2.2 Stepper Motor Speed
        3. 8.3.2.3 Decay Modes
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Functions

PIN TYPE DESCRIPTION
NAME PWP RGE
DRV8434E DRV8434P DRV8434E DRV8434P
ADECAY 21 21 16 16 I Decay mode setting pin. Set the decay mode for bridge A; quad-level pin.
AEN 25 — 20 — I Bridge A enable input. Logic high enables bridge A; logic low disables the bridge Hi-Z.
AIN1 — 25 — 20 I Bridge A PWM input. Logic controls the state of H-bridge A; internal pulldown.
AIN2 — 24 — 19 I Bridge B PWM input. Logic controls the state of H-bridge B; internal pulldown.
AOUT1 4, 5 4, 5 3 3 O Winding A output. Connect to motor winding.
AOUT2 6, 7 6, 7 4 4 O Winding A output. Connect to motor winding.
APH 24 — 19 — I Bridge A phase input. Logic high drives current from AOUT1 to AOUT2.
VREFA 18 18 13 13 I Reference voltage input. Voltage on this pin sets the full scale chopping current in H-bridge A.
BDECAY 20 20 15 15 I Decay mode setting pin. Set the decay mode for bridge B; quad-level pin.
BEN 23 — 18 — I Bridge B enable input. Logic high enables bridge B; logic low disables the bridge Hi-Z.
BIN1 — 23 — 18 I Bridge B PWM input. Logic controls the state of H-bridge B; internal pulldown.
BIN2 — 22 — 17 I Bridge B PWM input. Logic controls the state of H-bridge B; internal pulldown.
BOUT1 10, 11 10, 11 6 6 O Winding B output. Connect to motor winding.
BOUT2 8, 9 8, 9 5 5 O Winding B output. Connect to motor winding.
BPH 22 — 17 — I Bridge B phase input. Logic high drives current from BOUT1 to BOUT2.
VREFB 17 17 12 12 I Reference voltage input. Voltage on this pin sets the full scale chopping current in H-bridge B.
CPH 28 28 23 23 PWR Charge pump switching node. Connect a X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL.
CPL 27 27 22 22
GND 14 14 9 9 PWR Device ground. Connect to system ground.
TOFF 19 19 14 14 I Sets the decay mode off-time during current chopping; quad-level pin.
DVDD 15 15 10 10 PWR Logic supply voltage. Connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND.
VCP 1 1 24 24 O Charge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM.
VM 2, 13 2, 13 1, 8 1, 8 PWR Power supply. Connect to motor supply voltage and bypass to PGND with two 0.01-μF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM.
PGND 3, 12 3, 12 2, 7 2, 7 PWR Power ground. Connect to system ground.
nFAULT 16 16 11 11 O Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor.
nSLEEP 26 26 21 21 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. An nSLEEP low pulse clears faults.
PAD - - - - - Thermal pad. Connect to system ground.