SLOSE70 December 2020 DRV8434S
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES (VM, DVDD) | ||||||
IVM | VM operating supply current | ENABLE = 1, nSLEEP = 1, No motor load | 5 | 6.5 | mA | |
IVMQ | VM sleep mode supply current | nSLEEP = 0 | 2 | 4 | μA | |
tSLEEP | Sleep time | nSLEEP = 0 to sleep-mode |
120 | μs | ||
tRESET | nSLEEP reset pulse | nSLEEP low to clear fault |
20 |
40 | μs | |
tWAKE | Wake-up time | nSLEEP = 1 to output transition | 0.8 | 1.2 | ms | |
tON | Turn-on time | VM > UVLO to output transition | 0.8 | 1.2 | ms | |
tEN |
Enable time |
ENABLE = 0/1 to output transition |
5 | μs | ||
VDVDD | Internal regulator voltage | No external load, 6V < VVM < 48V | 4.75 | 5 | 5.25 | V |
No external load, VVM = 4.5V |
4.2 |
4.35 |
V | |||
CHARGE PUMP (VCP, CPH, CPL) | ||||||
VVCP | VCP operating voltage | 6V < VVM < 48V | VVM + 5 | V | ||
f(VCP) | Charge pump switching frequency | VVM > UVLO; nSLEEP = 1 | 360 | kHz | ||
LOGIC-LEVEL INPUTS (STEP, DIR, nSLEEP, nSCS, SCLK, SDI, ENABLE) | ||||||
VIL | Input logic-low voltage | 0 | 0.6 | V | ||
VIH | Input logic-high voltage | 1.5 | 5.5 | V | ||
VHYS | Input logic hysteresis | 150 | mV | |||
IIL1 | Input logic-low current (nSCS) | VIN = 0 V | 8 | 12 | μA | |
IIL | Input logic-low current (other pins) | VIN = 0 V | –1 | 1 | μA | |
IIH1 | Input logic-high current (nSCS) | VIN = DVDD | 500 | nA | ||
IIH | Input logic-high current (other pins) | VIN = 5 V | 100 | μA | ||
PUSH-PULL OUTPUT (SDO) | ||||||
RPD,SDO | Internal pull-down resistance | 5mA load, with respect to GND | 30 | 60 | Ω | |
RPU,SDO | Internal pull-up resistance | 5mA load, with respect to VSDO | 30 | 60 | Ω | |
ISDO | SDO Leakage Current | SDO = VSDO and 0V | -1 | 1 | μA | |
CONTROL OUTPUTS (nFAULT) | ||||||
VOL | Output logic-low voltage | IO = 5 mA | 0.5 | V | ||
IOH | Output logic-high leakage | –1 | 1 | μA | ||
MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | ||||||
RDS(ON) | High-side FET on resistance | TJ = 25 °C, IO = -1 A | 165 | 200 | mΩ | |
TJ = 125 °C, IO = -1 A | 250 | 300 | mΩ | |||
TJ = 150 °C, IO = -1 A | 280 | 350 | mΩ | |||
RDS(ON) | Low-side FET on resistance | TJ = 25 °C, IO = 1 A | 165 | 200 | mΩ | |
TJ = 125 °C, IO = 1 A | 250 | 300 | mΩ | |||
TJ = 150 °C, IO = 1 A | 280 | 350 | mΩ | |||
tSR | Output slew rate | VVM = 24 V, IO = 1 A, Between 10% and 90% | 240 | V/µs | ||
PWM CURRENT CONTROL (VREF) | ||||||
KV | Transimpedance gain | VREF = 3.3 V | 1.254 | 1.32 | 1.386 | V/A |
IVREF |
VREF leakage current | VREF = 3.3 V |
8.25 | µA | ||
tOFF | PWM off-time | TOFF = 00b | 7 | μs | ||
TOFF = 01b | 16 | |||||
TOFF = 10b | 24 | |||||
TOFF = 11b | 32 | |||||
ΔITRIP | Current trip accuracy | 0.25 A < IO < 0.5 A | –12 | 12 | % | |
0.5 A < IO < 1 A | –6 |
6 | ||||
1 A < IO < 2.5 A | –4 |
4 | ||||
IO,CH | AOUT and BOUT current matching | IO = 2.5 A | –2.5 | 2.5 | % | |
PROTECTION CIRCUITS | ||||||
VUVLO | VM UVLO lockout | VM falling, UVLO falling | 4.1 | 4.25 | 4.35 | V |
VM rising, UVLO rising | 4.2 | 4.35 | 4.45 | |||
VUVLO,HYS | Undervoltage hysteresis | Rising to falling threshold | 100 | mV | ||
VRST | VM UVLO reset | VM falling, device reset, no SPI communications | 3.9 | V | ||
VCPUV | Charge pump undervoltage | VCP falling; CPUV report | VVM + 2 | V | ||
IOCP | Overcurrent protection | Current through any FET | 4 | A | ||
tOCP | Overcurrent deglitch time | 2 | μs | |||
tRETRY | Overcurrent retry time | OCP_MODE = 1b | 4 | ms | ||
tOL | Open load detection time | EN_OL = 1b | 50 | ms | ||
IOL | Open load current threshold | EN_OL = 1b | 75 | mA | ||
TOTW | Overtemperature warning | Die temperature TJ | 135 | 150 | 165 | °C |
TOTSD | Thermal shutdown | Die temperature TJ | 150 | 165 | 180 | °C |
THYS_OTSD | Thermal shutdown hysteresis | Die temperature TJ | 20 | °C | ||
THYS_OTW | Overtemperature warning hysteresis | Die temperature TJ | 20 | °C |