SLOSE98A December   2022  – September 2023 DRV8461

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
      1. 6.5.1 SPI Timing Requirements
      2. 6.5.2 STEP and DIR Timing Requirements
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Interface of Operation
      2. 7.3.2  Stepper Motor Driver Current Ratings
        1. 7.3.2.1 Peak Current Rating
        2. 7.3.2.2 RMS Current Rating
        3. 7.3.2.3 Full-Scale Current Rating
      3. 7.3.3  PWM Motor Drivers
      4. 7.3.4  Microstepping Indexer
      5. 7.3.5  Indexer Output
        1. 7.3.5.1 nHOME Output
      6. 7.3.6  Automatic Microstepping Mode
      7. 7.3.7  Custom Microstepping Table
      8. 7.3.8  Current Regulation
        1. 7.3.8.1 Internal Reference Voltage
      9. 7.3.9  Standstill Power Saving Mode
      10. 7.3.10 Current Regulation Decay Modes
        1. 7.3.10.1 Slow Decay
        2. 7.3.10.2 Mixed Decay
        3. 7.3.10.3 Smart tune Dynamic Decay
        4. 7.3.10.4 Smart tune Ripple Control
        5. 7.3.10.5 PWM OFF Time
        6. 7.3.10.6 Current Regulation Blanking Time and Deglitch Time
      11. 7.3.11 Current Sensing with External Resistor
      12. 7.3.12 Silent step decay mode
      13. 7.3.13 Auto-torque Dynamic Current Adjustment
        1. 7.3.13.1 Auto-torque Learning Routine
        2. 7.3.13.2 Current Control Loop
        3. 7.3.13.3 PD Control Loop
      14. 7.3.14 Charge Pump
      15. 7.3.15 Linear Voltage Regulator
      16. 7.3.16 VCC Voltage Supply
      17. 7.3.17 Logic Level, Tri-Level and Quad-Level Pin Diagrams
      18. 7.3.18 Spread Spectrum
      19. 7.3.19 Protection Circuits
        1. 7.3.19.1  VM Undervoltage Lockout
        2. 7.3.19.2  VCP Undervoltage Lockout (CPUV)
        3. 7.3.19.3  Logic Supply Power on Reset (POR)
        4. 7.3.19.4  Overcurrent Protection (OCP)
          1. 7.3.19.4.1 Latched Shutdown
          2. 7.3.19.4.2 Automatic Retry
        5. 7.3.19.5  Stall Detection
        6. 7.3.19.6  Open-Load Detection (OL)
        7. 7.3.19.7  Overtemperature Warning (OTW)
        8. 7.3.19.8  Thermal Shutdown (OTSD)
          1. 7.3.19.8.1 Latched Shutdown
          2. 7.3.19.8.2 Automatic Retry
        9. 7.3.19.9  Supply voltage sensing
        10. 7.3.19.10 nFAULT Output
        11. 7.3.19.11 Fault Condition Summary
      20. 7.3.20 Device Functional Modes
        1. 7.3.20.1 Sleep Mode
        2. 7.3.20.2 Disable Mode
        3. 7.3.20.3 Operating Mode
        4. 7.3.20.4 nSLEEP Reset Pulse
        5. 7.3.20.5 Functional Modes Summary
    4. 7.4 Programming
      1. 7.4.1 Serial Peripheral Interface (SPI) Communication
        1. 7.4.1.1 SPI Format
        2. 7.4.1.2 SPI for Multiple Target Devices in Daisy Chain Configuration
        3. 7.4.1.3 SPI for Multiple Target Devices in Parallel Configuration
    5. 7.5 Register Maps
      1. 7.5.1 Status Registers
        1. 7.5.1.1 FAULT (address = 0x00) [Default = 00h]
        2. 7.5.1.2 DIAG1 (address = 0x01) [Default = 00h]
        3. 7.5.1.3 DIAG2 (address = 0x02) [Default = 00h]
        4. 7.5.1.4 DIAG3 (address = 0x03) [Default = 00h]
      2. 7.5.2 Control Registers
        1. 7.5.2.1  CTRL1 (address = 0x04) [Default = 0Fh]
        2. 7.5.2.2  CTRL2 (address = 0x05) [Default = 06h]
        3. 7.5.2.3  CTRL3 (address = 0x06) [Default = 38h]
        4. 7.5.2.4  CTRL4 (address = 0x07) [Default = 49h]
        5. 7.5.2.5  CTRL5 (address = 0x08) [Default = 03h]
        6. 7.5.2.6  CTRL6 (address = 0x09) [Default = 20h]
        7. 7.5.2.7  CTRL7 (address = 0x0A) [Default = FFh]
        8. 7.5.2.8  CTRL8 (address = 0x0B) [Default = 0Fh]
        9. 7.5.2.9  CTRL9 (address = 0x0C) [Default = 10h]
        10. 7.5.2.10 CTRL10 (address = 0x0D) [Default = 80h]
        11. 7.5.2.11 CTRL11 (address = 0x0E) [Default = FFh]
        12. 7.5.2.12 CTRL12 (address = 0x0F) [Default = 20h]
        13. 7.5.2.13 CTRL13 (address = 0x10) [Default = 10h]
        14. 7.5.2.14 CTRL14 (address = 0x3C) [Default = 58h]
      3. 7.5.3 Indexer Registers
        1. 7.5.3.1 INDEX1 (address = 0x11) [Default = 80h]
        2. 7.5.3.2 INDEX2 (address = 0x12) [Default = 80h]
        3. 7.5.3.3 INDEX3 (address = 0x13) [Default = 80h]
        4. 7.5.3.4 INDEX4 (address = 0x14) [Default = 82h]
        5. 7.5.3.5 INDEX5 (address = 0x15) [Default = B5h]
      4. 7.5.4 Custom Microstepping Registers
        1. 7.5.4.1 CUSTOM_CTRL1 (address = 0x16) [Default = 00h]
        2. 7.5.4.2 CUSTOM_CTRL2 (address = 0x17) [Default = 00h]
        3. 7.5.4.3 CUSTOM_CTRL3 (address = 0x18) [Default = 00h]
        4. 7.5.4.4 CUSTOM_CTRL4 (address = 0x19) [Default = 00h]
        5. 7.5.4.5 CUSTOM_CTRL5 (address = 0x1A) [Default = 00h]
        6. 7.5.4.6 CUSTOM_CTRL6 (address = 0x1B) [Default = 00h]
        7. 7.5.4.7 CUSTOM_CTRL7 (address = 0x1C) [Default = 00h]
        8. 7.5.4.8 CUSTOM_CTRL8 (address = 0x1D) [Default = 00h]
        9. 7.5.4.9 CUSTOM_CTRL9 (address = 0x1E) [Default = 00h]
      5. 7.5.5 Auto torque Registers
        1. 7.5.5.1  ATQ_CTRL1 (address = 0x1F) [Default = 00h]
        2. 7.5.5.2  ATQ_CTRL2 (address = 0x20) [Default = 00h]
        3. 7.5.5.3  ATQ_CTRL3 (address = 0x21) [Default = 00h]
        4. 7.5.5.4  ATQ_CTRL4 (address = 0x22) [Default = 20h]
        5. 7.5.5.5  ATQ_CTRL5 (address = 0x23) [Default = 00h]
        6. 7.5.5.6  ATQ_CTRL6 (address = 0x24) [Default = 00h]
        7. 7.5.5.7  ATQ_CTRL7 (address = 0x25) [Default = 00h]
        8. 7.5.5.8  ATQ_CTRL8 (address = 0x26) [Default = 00h]
        9. 7.5.5.9  ATQ_CTRL9 (address = 0x27) [Default = 00h]
        10. 7.5.5.10 ATQ_CTRL10 (address = 0x28) [Default = 08h]
        11. 7.5.5.11 ATQ_CTRL11 (address = 0x29) [Default = 0Ah]
        12. 7.5.5.12 ATQ_CTRL12 (address = 0x2A) [Default = FFh]
        13. 7.5.5.13 ATQ_CTRL13 (address = 0x2B) [Default = 05h]
        14. 7.5.5.14 ATQ_CTRL14 (address = 0x2C) [Default = 0Fh]
        15. 7.5.5.15 ATQ_CTRL15 (address = 0x2D) [Default = 00h]
        16. 7.5.5.16 ATQ_CTRL16 (address = 0x2E) [Default = FFh]
        17. 7.5.5.17 ATQ_CTRL17 (address = 0x2F) [Default = 00h]
        18. 7.5.5.18 ATQ_CTRL18 (address = 0x30) [Default = 00h]
      6. 7.5.6 Silent Step Registers
        1. 7.5.6.1 SS_CTRL1 (address = 0x31) [Default = 00h]
        2. 7.5.6.2 SS_CTRL2 (address = 0x32) [Default = 00h]
        3. 7.5.6.3 SS_CTRL3 (address = 0x33) [Default = 00h]
        4. 7.5.6.4 SS_CTRL4 (address = 0x34) [Default = 00h]
        5. 7.5.6.5 SS_CTRL5 (address = 0x35) [Default = FFh]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 Thermal Application
        1. 8.2.4.1 Power Dissipation
        2. 8.2.4.2 Conduction Loss
        3. 8.2.4.3 Switching Loss
        4. 8.2.4.4 Power Dissipation Due to Quiescent Current
        5. 8.2.4.5 Total Power Dissipation
        6. 8.2.4.6 Device Junction Temperature Estimation
  10. 9 Thermal Considerations
    1. 9.1 Thermal Pad
    2. 9.2 PCB Material Recommendation
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
    2. 10.2 Power Supplies
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1.1 SPI Format

The serial data input (SDI) word consists of a 16-bit word, with an 8 bit-command (A1), followed by 8-bit data (D1). The serial data output (SDO) word consists of 8 bits of status register with fault status indication (S1), followed by a report byte (R1). Figure 7-48 shows the data sequence between the controller and the SPI target driver.

GUID-60F9A3C8-FA4C-47D3-BC1D-FCF10F7B13EC-low.gifFigure 7-48 SPI Format - Standard "16-bit" Frame

A valid frame must meet the following conditions:

  • The SCLK pin must be low when the nSCS pin goes low and when the nSCS pin goes high.
  • The nSCS pin should be taken high for at least 500 ns between frames.
  • When the nSCS pin is asserted high, any signals at the SCLK and SDI pins are ignored, and the SDO pin is in the high-impedance state (Hi-Z).
  • A full 16 SCLK cycles must occur for a valid transaction for a standard frame, or alternately, for a daisy chainframe with "n" number of peripheral devices, 16 + (n x 16) SCLK cycles must occur for a valid transaction. Else, a frame error (SPI_ERROR) is reported and the data is ignored if it is a WRITE operation.
  • Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by thedevice on the subsequent falling edge of SCLK.
  • The most-significant bit (MSB) is shifted in and out first.
  • For a write command, the existing data in the register being written to is shifted out on the SDO pin following the 8-bit command data.

The SDI input data word is 16 bits long and consists of the following format, as shown in Table 7-31:

  • Command byte (first 8 bits)

    • MSB bit indicates frame type (bit B15 = 0 for standard frame).
    • Next to MSB bit, W0, indicates read or write operation (bit B14, write = 0, read = 1)
    • Followed by 6 address bits, A[5:0] (bits B13 through B8)

  • Data byte (last 8 bits)

    • Last 8 bits indicate data, D[7:0] (bits B7 through B0). For a read operation, these bits are typically set to null values, while for a write operation, these bits have the data value for the addressed register.

Table 7-31 SDI - Standard Frame Format

R/W

ADDRESSDATA

B15

B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0

0

W0

A5

A4A3A2A1A0D7D6D5D4D3D2D1D0

The SDO output data word is 16 bits long and consists of the following format, as shown in Table 7-32:

  • Status byte (first 8 bits)

    • 2 MSB bits are forced high (B15, B14 = 1).

    • Following 6 bits are from the FAULT register (bits B13 through B8)

  • Report byte (last 8 bits)

    • The last 8 bits (B7:B0) are either the data currently in the register being read for a read operation (W0 =1), or, existing data in the register being written to for a write command (W0 = 0).

Table 7-32 SDO Output Data Word Format
STATUSREPORT
B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0
11

UVLO

CPUV

OCP

STL

TF

OL

D7D6D5D4D3D2D1D0