SLOSE98A December 2022 – September 2023 DRV8461
PRODUCTION DATA
For an ambient temperature of TA and total power dissipation (PTOT), the junction temperature (TJ) is calculated as -
TJ = TA + (PTOT x RθJA)
Considering a JEDEC standard 4-layer PCB, the junction-to-ambient thermal resistance (RθJA) is 23.2 °C/W for the DDW package and 25.2 °C/W for the PWP package.
Assuming 25°C ambient temperature, the junction temperature for the DDW package is calculated as shown below -
The junction temperature for the PWP package is calculated as shown below -
As explained in Section 8.2.4.2, for more accurate calculation, consider the dependency of on-resistance of FETs with device junction temperature shown in Section 6.6.
For example,
At 100.4 °C junction temperature, the on-resistance will likely increase by a factor of 1.3 compared to the on-resistance at 25 °C.
The initial estimate of conduction loss was 2.7 W.
New estimate of conduction loss will therefore be 2.7 W x 1.3 = 3.51 W.
New estimate of the total power loss will accordingly be 4.058 W.
New estimate of junction temperature for the DDW package will be 119.1 °C.
Further iterations are unlikely to increase the junction temperature estimate by significant amount.