SLOSE98A December 2022 – September 2023 DRV8461
PRODUCTION DATA
Table 7-33 lists the memory-mapped registers for the device. All register addresses not listed in Table 7-33 should be considered as reserved locations and the register contents must not be modified.
Register | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Type | Address |
---|---|---|---|---|---|---|---|---|---|---|
FAULT | FAULT | SPI_ERROR | UVLO | CPUV | OCP | STL | TF | OL | R | 0x00 |
DIAG1 | OCP_LS2_B | OCP_HS2_B | OCP_LS1_B | OCP_HS1_B | OCP_LS2_A | OCP_HS2_A | OCP_LS1_A | OCP_HS1_A | R | 0x01 |
DIAG2 | STSL | OTW | OTS | STL_LRN_OK | STALL | LRN_DONE | OL_B | OL_A | R | 0x02 |
RSVD | NHOME | CNT_OFLW | CNT_UFLW | RSVD | NPOR | RSVD | R | 0x03 | ||
CTRL1 | EN_OUT | SR | IDX_RST | TOFF [1:0] | DECAY [2:0] | RW | 0x04 | |||
CTRL2 | DIR | STEP | SPI_DIR | SPI_STEP | MICROSTEP_MODE [3:0] | RW | 0x05 | |||
CTRL3 | CLR_FLT | LOCK [2:0] | TOCP | OCP_MODE | OTSD_MODE | OTW_REP | RW | 0x06 | ||
CTRL4 | TBLANK_TIME[1:0] | STL_LRN | EN_STL | STL_REP | STL_FRQ | STEP_FRQ_TOL[1:0] | RW | 0x07 | ||
CTRL5 | STALL_TH [7:0] | RW | 0x08 | |||||||
CTRL6 | RC_RIPPLE[1:0] | DIS_SSC | TRQ_SCALE | STALL_TH[11:8] | RW | 0x09 | ||||
CTRL7 | TRQ_COUNT [7:0] | R | 0x0A | |||||||
CTRL8 | RSVD | TRQ_COUNT[11:8] | R | 0x0B | ||||||
EN_OL | OL_MODE | OL_T[1:0] | STEP_EDGE | RES_AUTO[1:0] | EN_AUTO | RW | 0x0C | |||
ISTSL[7:0] | RW | 0x0D | ||||||||
TRQ_DAC[7:0] | RW | 0x0E | ||||||||
EN_STSL | TSTSL_FALL[3:0] | RSVD | RW | 0x0F | ||||||
TSTSL_DLY[5:0] | VREF_INT_EN | RSVD | RW | 0x10 | ||||||
CUR_A_POS[7:0] | R | 0x11 | ||||||||
CUR_A_SIGN | RSVD | R | 0x12 | |||||||
CUR_B_POS[7:0] | R | 0x13 | ||||||||
CUR_B_SIGN | RSVD | CUR_A[1:0] | R | 0x14 | ||||||
CUR_A[9:2] | R | 0x15 | ||||||||
CUSTOM_CTRL1 | RSVD | EN_CUSTOM | RW | 0x16 | ||||||
CUSTOM_CTRL2 | CUSTOM_CURRENT1[7:0] | RW | 0x17 | |||||||
CUSTOM_CTRL3 | CUSTOM_CURRENT2[7:0] | RW | 0x18 | |||||||
CUSTOM_CTRL4 | CUSTOM_CURRENT3[7:0] | RW | 0x19 | |||||||
CUSTOM_CTRL5 | CUSTOM_CURRENT4[7:0] | RW | 0x1A | |||||||
CUSTOM_CTRL6 | CUSTOM_CURRENT5[7:0] | RW | 0x1B | |||||||
CUSTOM_CTRL7 | CUSTOM_CURRENT6[7:0] | RW | 0x1C | |||||||
CUSTOM_CTRL8 | CUSTOM_CURRENT7[7:0] | RW | 0x1D | |||||||
CUSTOM_CTRL9 | CUSTOM_CURRENT8[7:0] | RW | 0x1E | |||||||
ATQ_CNT[7:0] | R | 0x1F | ||||||||
ATQ_CTRL2 | ATQ_CNT[10:8] | RSVD | ATQ_LRN_CONST1[10:8] | RW | 0x20 | |||||
ATQ_CTRL3 | ATQ_LRN_CONST1[7:0] | RW | 0x21 | |||||||
ATQ_CTRL4 | ATQ_LRN_MIN_CURRENT[4:0] | ATQ_LRN_CONST2[10:8] | RW | 0x22 | ||||||
ATQ_CTRL5 | ATQ_LRN_CONST2[7:0] | RW | 0x23 | |||||||
ATQ_CTRL6 | ATQ_UL[7:0] | RW | 0x24 | |||||||
ATQ_CTRL7 | ATQ_LL[7:0] | RW | 0x25 | |||||||
ATQ_CTRL8 | KP[7:0] | RW | 0x26 | |||||||
ATQ_CTRL9 | RSVD | KD[3:0] | RW | 0x27 | ||||||
ATQ_CTRL10 | ATQ_EN | LRN_START | ATQ_FRZ[2:0] | ATQ_AVG[2:0] | RW | 0x28 | ||||
ATQ_CTRL11 | ATQ_TRQ_MIN[7:0] | RW | 0x29 | |||||||
ATQ_CTRL12 | ATQ_TRQ_MAX[7:0] | RW | 0x2A | |||||||
ATQ_CTRL13 | ATQ_D_THR[7:0] | RW | 0x2B | |||||||
ATQ_CTRL14 | RSVD | RW | 0x2C | |||||||
ATQ_CTRL15 | ATQ_ERROR_TRUNCATE[3:0] | ATQ_LRN_STEP[1:0] | ATQ_LRN_CYCLE_SELECT[1:0] | RW | 0x2D | |||||
ATQ_CTRL16 | ATQ_TRQ_DAC[7:0] | R | 0x2E | |||||||
ATQ_CTRL17 | RSVD | VM_SCALE | RSVD | RW | 0x2F | |||||
ATQ_CTRL18 | RSVD | RW | 0x30 | |||||||
SS_CTRL1 | SS_SMPL_SEL[1:0] | RSVD | SS_PWM_FREQ[1:0] | RSVD | EN_SS | RW | 0x31 | |||
SS_CTRL2 | SS_KP[7:0] | RW | 0x32 | |||||||
SS_CTRL3 | SS_KI[7:0] | RW | 0x33 | |||||||
SS_CTRL4 | RSVD | SS_KI_DIV_SEL[2:0] | RSVD | SS_KP_DIV_SEL[2:0] | RW | 0x34 | ||||
SS_CTRL5 | SS_THR[7:0] | RW | 0x35 | |||||||
CTRL 14 | VM_ADC[4:0] | RSVD | RW | 0x3C |
Complex bit access types are encoded to fit into small table cells. Table 7-34 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |