Built-in indexer logic in the device allows a number of different step modes. The MICROSTEP_MODE bits in the SPI register or the M0 and M1 pins are used to configure the step mode as shown in Table 7-5.

When operating with SPI, the device allows stepping and direction change over SPI interface as well, as shown in Table 7-6. Four bits are dedicated for this purpose -

Table 7-7 shows the relative current and step directions for full-step (71% current), 1/2 step, 1/4 step and 1/8 step operation for the case when DIR pin is logic high or DIR bit is '1'. Higher microstepping resolutions follow the same pattern. The AOUT current is the sine of the electrical angle and the BOUT current is the cosine of the electrical angle. Positive current is defined as current flowing from the xOUT1 pin to the xOUT2 pin while driving.

Table 7-8 shows the full step operation with 100% full-scale current for the DIR = 1 case. This stepping mode consumes more power than full-step mode with 71% current, but provides a higher torque at high motor RPM.

Table 7-9 shows the noncircular 1/2–step operation for the DIR = 1 case. This stepping mode consumes more power than circular 1/2-step operation, but provides a higher torque at high motor RPM.

When operating with the SPI, depending on the STEP_EDGE bit, STEP active edge can be either rising edge or both rising and falling edge, as shown in Table 7-10. When configured with H/W interface, the STEP active edge is only the rising edge. For applications that need to run at high input STEP rate, configuring both edges as active edge reduces controller overhead by half, because the input STEP rate is effectively doubled.

At each active edge of the STEP input the indexer advances to the next state in the table. The direction shown is with the DIR pin logic high. If the DIR pin is logic low, the sequence table is reversed. If the step mode is changed dynamically while stepping, the indexer advances to the next valid state for the new step mode setting at the active edge of STEP.

After power-up, after exiting logic undervoltage lockout, or after exiting sleep mode, the indexer moves to an initial excitation state (home position) of 45° electrical angle, corresponding to 71% of full-scale current in both coils. All the registers are restored to their deafult values in such scenario.

When operating with the SPI, if the IDX_RST bit is 1b, it resets the indexer to 45° electrical angle as shown in Figure 7-5, but the contents of the memory map registers do not change.

Figure 7-5 Indexer reset. Traces from top to bottom: AOUT2, AOUT1, STEP, coil B current, coil A current, nSCS

If the STEP input frequency is jittery, the device filters the signal for the purpose of stall detection. The FRQ_CHG and STEP_FRQ_TOL bits program the filter setting, as shown in Table 7-11. 2% filtering means up to 2% jitter around the center frequency will be filtered out to generate a clean STEP signal for internal circuits to detect motor stall.