SLVSCX5B March   2015  – July 2015 DRV8701

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
      2. 7.3.2  Half-Bridge Operation
      3. 7.3.3  Current Regulation
      4. 7.3.4  Amplifier Output SO
        1. 7.3.4.1 SNSOUT
      5. 7.3.5  PWM Motor Gate Drivers
      6. 7.3.6  IDRIVE Pin
      7. 7.3.7  Dead Time
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Overcurrent VDS Monitor
      10. 7.3.10 Charge Pump
      11. 7.3.11 LDO Voltage Regulators
      12. 7.3.12 Gate Drive Clamp
      13. 7.3.13 Protection Circuits
        1. 7.3.13.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.13.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.13.3 Overcurrent Protection (OCP)
        4. 7.3.13.4 Pre-Driver Fault (PDF)
        5. 7.3.13.5 Thermal Shutdown (TSD)
      14. 7.3.14 Reverse Supply Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating DRV8701 and H-Bridge on Separate Supplies
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Brushed-DC Motor Control
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External FET Selection
          2. 8.2.1.2.2 IDRIVE Configuration
          3. 8.2.1.2.3 Current Chopping Configuration
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternate Application
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 IDRIVE Configuration
        2. 8.2.3.2 VM Boost Voltage
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Bypass the VM pin to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane connection to the device GND pin.

Bypass the VM pin to ground using a bulk capacitor rated for VM. This component may be an electrolytic. This capacitance must be at least 10 µF. The bulk capacitor should be placed to minimize the distance of the high-current path through the external FETs.  The connecting metal trace widths should be as wide as possible, and numerous vias should be used when connecting PCB layers.  These practices minimize inductance and allow the bulk capacitor to deliver high current.

Place a low-ESR ceramic capacitor in between the CPL and CPH pins. The value for this component is 0.1 µF rated for VM. Place this component as close to the pins as possible.

Place a low-ESR ceramic capacitor in between the VM and VCP pins. The value for this component is 1 µF rated for 16 V. Place this component as close to the pins as possible.

Bypass AVDD and DVDD to ground with ceramic capacitors rated at 6.3 V. Place these bypassing capacitors as close to the pins as possible.

If desired, align the external NMOS FETs as shown in Figure 42 to facilitate layout. Route the SH2 and SH1 nets to the motor.

Use separate traces to connect the SP and SN pins to the RSENSE terminals.

10.2 Layout Example

DRV8701 layout_ex_LVSCX5.gifFigure 42. Layout Recommendation