SLVSDR9E October 2016 – January 2021 DRV8702-Q1 , DRV8703-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power supply voltage | VM | –0.3 | 47 | V |
Charge pump voltage | VCP, CPH | –0.3 | VVM + 12 | V |
Charge pump negative switching pin | CPL | –0.3 | VVM | V |
Internal logic regulator voltage | DVDD | –0.3 | 3.8 | V |
Internal analog regulator voltage | AVDD | –0.3 | 5.75 | V |
Drain pin voltage | VDRAIN | –0.3 | 47 | V |
Voltage difference between supply and VDRAIN | VM – VDRAIN | –10 | 10 | V |
Control pin voltage | IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, VDS, MODE, nSCS, SCLK, SDI, SDO, nWDFLT | –0.3 | 5.75 | V |
High-side gate pin voltage | GH1, GH2 | –0.3 | VVM + 12 | V |
Low-side gate pin voltage | GL1, GL2 | –0.3 | 12 | V |
Continuous phase-node pin voltage | SH1, SH2 | –1.2 | VVM + 1.2 | V |
Pulsed 10-µs phase-node pin voltage | SH1, SH2 | –2 | VVM + 2 | V |
Continuous shunt amplifier input pin voltage | SP, SL2 | –0.5 | 1.2 | V |
SN | –0.3 | 0.3 | V | |
Pulsed 10-µs shunt amplifier input pin voltage | SP, SL2 | –1 | 1.2 | V |
Shunt amplifier output pin voltage | SO | –0.3 | 5.75 | V |
Shunt amplifier output pin current | SO | 0 | 5 | mA |
Maximum current, limit current with external series resistor | VDRAIN | –2 | 2 | mA |
Open-drain output current | nFAULT, SDO, nWDFLT | 0 | 10 | mA |
Gate pin source current | GH1, GL1, GH2, GL2 | 0 | 250 | mA |
Gate pin sink current | GH1, GL1, GH2, GL2 | 0 | 500 | mA |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |