SLVSDR9E October   2016  – January 2021 DRV8702-Q1 , DRV8703-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Switching Characteristics
    8.     15
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
        1. 7.3.1.1 Logic Tables
      2. 7.3.2  MODE Pin
      3. 7.3.3  nFAULT Pin
      4. 7.3.4  Current Regulation
      5. 7.3.5  Amplifier Output (SO)
        1. 7.3.5.1 SO Sample and Hold Operation
      6. 7.3.6  PWM Motor Gate Drivers
        1. 7.3.6.1 Miller Charge (QGD)
      7. 7.3.7  IDRIVE Pin (DRV8702-Q1 Only)
      8. 7.3.8  Dead Time
      9. 7.3.9  Propagation Delay
      10. 7.3.10 Overcurrent VDS Monitor
      11. 7.3.11 VDS Pin (DRV8702-Q1 Only)
      12. 7.3.12 Charge Pump
      13. 7.3.13 Gate Drive Clamp
      14. 7.3.14 Protection Circuits
        1. 7.3.14.1 VM Undervoltage Lockout (UVLO2)
        2. 7.3.14.2 Logic Undervoltage (UVLO1)
        3. 7.3.14.3 VCP Undervoltage Lockout (CPUV)
        4. 7.3.14.4 Overcurrent Protection (OCP)
        5. 7.3.14.5 Gate Driver Fault (GDF)
        6. 7.3.14.6 Thermal Shutdown (TSD)
        7. 7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)
        8. 7.3.14.8 Reverse Supply Protection
      15. 7.3.15 Hardware Interface
        1. 7.3.15.1 IDRIVE (6-level input)
        2. 7.3.15.2 VDS (6-Level Input)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 Serial Peripheral Interface (SPI)
        2. 7.5.1.2 SPI Format
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External FET Selection
        2. 8.2.2.2 IDRIVE Configuration
        3. 8.2.2.3 VDS Configuration
        4. 8.2.2.4 Current Chopping Configuration
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.14.7 Watchdog Fault (WDFLT, DRV8703-Q1 Only)

An MCU watchdog function can be enabled to ensure that the external controller that is instructing the DRV8703-Q1 device is active and in a known state. The SPI watchdog must be enabled by writing a 1 to the WD_EN bit through the SPI (disabled by default, bit is 0). When the watchdog is enabled, an internal timer starts to count down to an interval set by the WD_DLY bits. The register address 0x00 must be read by the MCU within the interval set by the WD_DLY bit to reset the watchdog. If the timer is allowed to expire, the nWDFLT pin is enabled. When the nWDFLT pin is enabled the following occurs:

  • The nWDFLT pin goes low for 64 µs.
  • The nFAULT pin is asserted.
  • The WD_EN bit is cleared.
  • The drivers are disabled.

The WDFLT bit remains asserted, and operation is halted until the CLR_FLT bit has been written to 1.

Table 7-9 lists the fault responses of the device under the fault conditions.

Table 7-9 Fault Response
FAULTCONDITIONH-BRIDGECHARGE PUMPAVDDDVDDRECOVERY
VM undervoltage
(UVLO)		VVM ≤ V(UVLOx)
(5.45 V, max)		DisabledDisabledDisabledOperatingVVM ≥ V(UVLOx)
(5.65 V, max)
VCP undervoltage
(CPUV)		VVCP ≤ V(CP_UV)
(VVM + 1.5, typ)		DisabledOperatingOperatingOperatingVVCP ≥ V(CP_UV)
(VVM + 1.5, typ)
External FET overload
(OCP)		VDS ≥ VDS(OCP)
VSP – VSN > 1 V		DisabledOperatingOperatingOperatingt(RETRY)
Gate driver fault
(GDF)		Gate voltage unchanged after t(DRIVE)DisabledOperatingOperatingOperatingt(RETRY)
Watchdog fault
(WDFLT)		Watchdog timer expiresDisabledOperatingOperatingOperatingCLR_FLT bit
Thermal shutdown
(TSD)		TJ ≥ TSD (150°C, min)DisabledDisabledDisabledOperatingTJ ≤ TSD – Thys
(Thys is typically 20°C)