SLLSFA7A July   2020  – April 2021 DRV8706-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Descriptions
  4. 4 Revision History
  5. 5 Pin Configuration
    1.     DRV8706-Q1_RHB Package (VQFN) Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 External Components
      2. 7.3.2 Device Interface Variants
        1. 7.3.2.1 Serial Peripheral Interface (SPI)
        2. 7.3.2.2 Hardware (H/W)
      3. 7.3.3 Input PWM Modes
        1. 7.3.3.1 Half-Bridge Control
        2. 7.3.3.2 H-Bridge Control
        3. 7.3.3.3 Split HS and LS Solenoid Control
      4. 7.3.4 Smart Gate Driver
        1. 7.3.4.1 Functional Block Diagram
        2. 7.3.4.2 Slew Rate Control (IDRIVE)
        3. 7.3.4.3 Gate Drive State Machine (TDRIVE)
      5. 7.3.5 Doubler (Single-Stage) Charge Pump
      6. 7.3.6 Wide Common Mode Differential Current Shunt Amplifier
      7. 7.3.7 Pin Diagrams
        1. 7.3.7.1 Logic Level Input Pin (DRVOFF, IN1/EN, IN2/PH, nHIZx, nSLEEP, nSCS, SCLK, SDI)
        2. 7.3.7.2 Logic Level Push Pull Output (SDO)
        3. 7.3.7.3 Logic Level Open Drain Output (nFAULT)
        4. 7.3.7.4 Quad-Level Input (GAIN)
        5. 7.3.7.5 Six-Level Input (IDRIVE, VDS)
      8. 7.3.8 Protection and Diagnostics
        1. 7.3.8.1  Gate Driver Disable and Enable (DRVOFF and EN_DRV)
        2. 7.3.8.2  Fault Reset (CLR_FLT)
        3. 7.3.8.3  DVDD Logic Supply Power on Reset (DVDD_POR)
        4. 7.3.8.4  PVDD Supply Undervoltage Monitor (PVDD_UV)
        5. 7.3.8.5  PVDD Supply Overvoltage Monitor (PVDD_OV)
        6. 7.3.8.6  VCP Charge Pump Undervoltage Lockout (VCP_UV)
        7. 7.3.8.7  MOSFET VDS Overcurrent Protection (VDS_OCP)
        8. 7.3.8.8  Gate Driver Fault (VGS_GDF)
        9. 7.3.8.9  Thermal Warning (OTW)
        10. 7.3.8.10 Thermal Shutdown (OTSD)
        11. 7.3.8.11 Offline Short Circuit and Open Load Detection (OOL and OSC)
        12. 7.3.8.12 Fault Detection and Response Summary Table
    4. 7.4 Device Function Modes
      1. 7.4.1 Inactive or Sleep State
      2. 7.4.2 Standby State
      3. 7.4.3 Operating State
    5. 7.5 Programming
      1. 7.5.1 SPI Interface
      2. 7.5.2 SPI Format
      3. 7.5.3 SPI Interface for Multiple Slaves
        1. 7.5.3.1 SPI Interface for Multiple Slaves in Daisy Chain
    6. 7.6 Register Maps
      1. 7.6.1 STATUS Registers
      2. 7.6.2 CONTROL Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Gate Driver Configuration
          1. 8.2.2.1.1 VCP Load Calculation Example
          2. 8.2.2.1.2 IDRIVE Calculation Example
        2. 8.2.2.2 Current Shunt Amplifier Configuration
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
      2. 10.1.2 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Driver power supply pin voltage PVDD –0.3 40 V
MOSFET drain sense pin voltage DRAIN –0.3 40 V
Voltage difference between ground pins AGND, GND –0.3 0.3 V
Charge pump pin voltage VCP –0.3 55 V
Charge pump high-side pin voltage CPH VPVDD – 0.3 VVCP + 0.3 V
Charge pump low-side pin voltage CPL –0.3 VPVDD + 0.3 V
Digital power supply pin voltage DVDD –0.3 5.75 V
Logic pin voltage DRVOFF, GAIN, IDRIVE, IN1/EN, IN2/PH, MODE, nHIZx, nSLEEP, nFAULT, nSCS, SCLK, SDI, VDS –0.3 5.75 V
Output logic pin voltage SDO –0.3 VDVDD + 0.3 V
High-side gate drive pin voltage GHx(2) –2 VVCP + 0.3 V
Transient 1-µs high-side gate drive pin voltage –5 VVCP + 0.3
High-side gate drive pin voltage with respect to SHx –0.3 13.5
High-side sense pin voltage SHx(2) –2 40 V
Transient 1-µs high-side sense pin voltage –5 40
Low-side gate drive pin voltage GLx(2) –2 13.5 V
Transient 1-µs low-side gate drive pin voltage –3 13.5
Low-side gate drive pin voltage with respect to SLx –0.3 13.5
Low-side sense pin voltage SLx(2) –2 2 V
Transient 1-µs low-side sense pin voltage –3 3
Peak gate drive current GHx, GLx Internally Limited Internally Limited mA
Amplfier power supply and reference pin voltage AREF –0.3 5.75 V
Amplifier input pin voltage SN, SP –2 VVCP + 0.3 V
Transient 1-µs amplifier input pin voltage –5 VVCP + 0.3
Amplifier input differential voltage SN, SP –5.75 5.75 V
Amplifier output pin voltage SO –0.3 VAREF + 0.3 V
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) PVDD and DRAIN with respect to GHx, SHx, GLx, or SLx should not exceed 40-V. When PVDD or DRAIN are greater than 35-V, negative voltage on GHx, SHx, GLx, and SLx should be limited to ensure this rating is not exceeded. When PVDD and DRAIN are less than 35-V, the full negative voltage rating of GHx, SHx, GLx, and SLx is available.