SLVSC40H June   2013  – May 2020 DRV8711

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Decay Modes
      6. 7.3.6  Blanking Time
      7. 7.3.7  Predrivers
      8. 7.3.8  Configuring Predrivers
      9. 7.3.9  External FET Selection
      10. 7.3.10 Stall Detection
        1. 7.3.10.1 Internal Stall Detection
        2. 7.3.10.2 External Stall Detection
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 Overcurrent Protection (OCP)
        2. 7.3.11.2 Predriver Fault
        3. 7.3.11.3 Thermal Shutdown (TSD)
        4. 7.3.11.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET and SLEEPn Operation
      2. 7.4.2 Microstepping Drive Current
    5. 7.5 Programming
      1. 7.5.1 Serial Data Format
    6. 7.6 Register Maps
      1. 7.6.1 Control Registers
      2. 7.6.2 CTRL Register (Address = 0x00)
      3. 7.6.3 TORQUE Register (Address = 0x01)
      4. 7.6.4 OFF Register (Address = 0x02)
      5. 7.6.5 BLANK Register (Address = 0x03)
      6. 7.6.6 DECAY Register (Address = 0x04)
      7. 7.6.7 STALL Register (Address = 0x05)
      8. 7.6.8 DRIVE Register (Address = 0x06)
      9. 7.6.9 STATUS Register (Address = 0x07)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sense Resistor
      2. 8.1.2 Optional Series Gate Resistor
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Set Step Rate
        2. 8.2.2.2 Calculate Current Regulation
        3. 8.2.2.3 Support External FETs
        4. 8.2.2.4 Pick Decay Mode
        5. 8.2.2.5 Config Stall Detection
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DCP PowerPAD™ Package
38-Pin HTSSOP
Top View
DRV8711 pin_out_SLVSC40.gif

Pin Functions

PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS OR CONNECTIONS
NAME NO.
POWER AND GROUND
GND 5, 29, 38, PPAD — Device ground All pins must be connected to ground
VM 4 — Bridge A power supply Connect to motor supply voltage. Bypass to GND with a 0.01-μF ceramic capacitor plus a 100-μF electrolytic capacitor.
VINT 7 — Internal logic supply voltage Logic supply voltage. Bypass to GND with a 1-μF 6.3-V X7R ceramic capacitor.
V5 6 O 5-V regulator output 5-V linear regulator output. Bypass to GND with a 0.1-μF 10-V X7R ceramic capacitor.
CP1 1 IO Charge pump flying capacitor Connect a 0.1-μF X7R capacitor between CP1 and CP2. Voltage rating must be greater than applied VM voltage.
CP2 2 IO Charge pump flying capacitor
VCP 3 IO High-side gate drive voltage Connect a 1-μF 16-V X7R ceramic capacitor to VM
CONTROL
SLEEPn 8 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode
STEP/AIN1 10 I Step input/Bridge A IN1 Indexer mode: Rising edge causes the indexer to move one step.
External PWM mode: controls bridge A OUT1 Internal pulldown.
DIR/AIN2 11 I Direction input/Bridge A IN2 Indexer mode: Level sets the direction of stepping.
External PWM mode: controls bridge A OUT2 Internal pulldown.
BIN1 12 I Bridge B IN1 Indexer mode: No function
External PWM mode: controls bridge B OUT1 Internal pulldown.
BIN2 13 I Bridge B IN2 Indexer mode: No function
External PWM mode: controls bridge B OUT2 Internal pulldown.
RESET 9 I Reset input Active-high reset input initializes all internal logic and disables the H-bridge outputs. Internal pulldown.
SERIAL INTERFACE
SCS 16 I Serial chip select input Active high to enable serial data transfer. Active low to complete the transaction. Internal pulldown.
SCLK 14 I Serial clock input Rising edge clocks data into part for write operations. Falling edge clocks data out of part for read operations. Internal pulldown.
SDATI 15 I Serial data input Serial data input from controller. Internal pulldown.
SDATO 17 OD Serial data output Serial data output to controller. Open-drain output requires external pullup.
STATUS
STALLn/
BEMFVn		 19 OD Stall/Back EMF valid Internal stall detect mode: logic low when motor stall detected.
External stall detect mode: Active low when valid back EMF measurement is ready.
Open-drain output requires external pullup.
FAULTn 18 OD Fault Logic low when in fault condition. Open-drain output requires external pullup.
Faults: OCP, PDF, OTS, UVLO
BEMF 20 O Back EMF Analog output voltage represents motor back EMF. Place a 1-nF low-leakage capacitor to ground on this pin.
OUTPUTS
A1HS 36 O Bridge A out 1 HS gate Connect to gate of HS FET for bridge A out 1
AOUT1 37 I Bridge A output 1 Connect to output node of external FETs of bridge A out 1
A1LS 35 O Bridge A out 1 LS gate Connect to gate of LS FET for bridge A out 1
A2HS 31 O Bridge A out 2 HS gate Connect to gate of HS FET for bridge A out 2
AOUT2 30 I Bridge A output 2 Connect to output node of external FETs of bridge A out 2
A2LS 32 O Bridge A out 2 LS gate Connect to gate of LS FET for bridge A out 2
AISENP 34 I Bridge A Isense + in Connect to current sense resistor for bridge A
AISENN 33 I Bridge A Isense – in Connect to ground at current sense resistor for bridge A
B1HS 27 O Bridge B out 1 HS gate Connect to gate of HS FET for bridge B out 1
BOUT1 28 I Bridge B output 1 Connect to output node of external FETs of bridge B out 1
B1LS 26 O Bridge B out 1 LS gate Connect to gate of LS FET for bridge B out 1
B2HS 22 O Bridge B out 2 HS gate Connect to gate of HS FET for bridge B out 2
BOUT2 21 I Bridge B output 2 Connect to output node of external FETs of bridge B out 2
B2LS 23 O Bridge B out 2 LS gate Connect to gate of LS FET for bridge B out 2
BISENP 25 I Bridge B Isense + in Connect to current sense resistor for bridge B
BISENN 24 I Bridge B Isense – in Connect to ground at current sense resistor for bridge B
(1) Directions: I = input, O = output, OZ = 3-state output, OD = open-drain output, IO = input/output