SLVSC40H June   2013  – May 2020 DRV8711

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Decay Modes
      6. 7.3.6  Blanking Time
      7. 7.3.7  Predrivers
      8. 7.3.8  Configuring Predrivers
      9. 7.3.9  External FET Selection
      10. 7.3.10 Stall Detection
        1. 7.3.10.1 Internal Stall Detection
        2. 7.3.10.2 External Stall Detection
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 Overcurrent Protection (OCP)
        2. 7.3.11.2 Predriver Fault
        3. 7.3.11.3 Thermal Shutdown (TSD)
        4. 7.3.11.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET and SLEEPn Operation
      2. 7.4.2 Microstepping Drive Current
    5. 7.5 Programming
      1. 7.5.1 Serial Data Format
    6. 7.6 Register Maps
      1. 7.6.1 Control Registers
      2. 7.6.2 CTRL Register (Address = 0x00)
      3. 7.6.3 TORQUE Register (Address = 0x01)
      4. 7.6.4 OFF Register (Address = 0x02)
      5. 7.6.5 BLANK Register (Address = 0x03)
      6. 7.6.6 DECAY Register (Address = 0x04)
      7. 7.6.7 STALL Register (Address = 0x05)
      8. 7.6.8 DRIVE Register (Address = 0x06)
      9. 7.6.9 STATUS Register (Address = 0x07)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sense Resistor
      2. 8.1.2 Optional Series Gate Resistor
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Set Step Rate
        2. 8.2.2.2 Calculate Current Regulation
        3. 8.2.2.3 Support External FETs
        4. 8.2.2.4 Pick Decay Mode
        5. 8.2.2.5 Config Stall Detection
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.3 Support External FETs

It is critical to ensure that any external FETs used can support the PWM current chopping frequency desired. Equation 3 is used to calculate the maximum FET driving capability of the DRV8711:

Equation 9. DRV8711 EQ3_Qg_slva632.gif

In Equation 3, 2 × DTIME + TBLANK + TOFF is the worst-case scenario (smallest time period) for PWM current chopping (1/ƒPWM). Since the PWM current chopping frequency is not fixed, the desired ƒPWM only gives an estimate on the worst-case FET driving capacity.

DTIME is the dead-time inserted between turning off a low-side FET and turning on a high-side FET, or vice versa. During this time, both FETs are in High-Z, and current is conducted through the body diodes in asynchronous decay. It is recommended to leave DTIME as its default value unless the stepping speed is very high.

CTRL Register Address = 0x00h
Bit Name Size R/W Default Description
11-10 DTIME 2 R/W 11 Dead time set
00: 400 ns dead time
01: 450 ns dead time
10: 650 ns dead time
11: 850 ns dead time

TBLANK is the blanking time during PWM current chopping. This sets the minimum drive time (current is increasing) during the PWM cycle. At the beginning of the PWM cycle, the current trip value is ignored for TBLANK. In auto mixed decay mode, TBLANK is also the fast decay time if the current is higher than the current chopping level after the drive time. This value is explained more in the Blanking time section.

BLANK Register Address = 0x03h
Bit Name Size R/W Default Description
7-0 TBLANK 8 R/W 0x80h Sets current trip blanking time, in increments of 20 ns
0x00h: 1.00 µs
…
0x32h: 1.00 µs
0x33h: 1.02 µs
…
0xFEh: 5.10 µs
0xFFh: 5.12 µs
Also sets minimum on-time of PWM

TOFF sets the time that the driver is in a decay mode after the drive phase of PWM current chopping. This value is explained more in the Decay Modes section.

OFF Register Address = 0x02h
Bit Name Size R/W Default Description
7-0 TOFF 8 R/W 0x30H Sets fixed off time, in increments of 500 ns
0x00h: 500 ns
0xFFh: 128 µs

The registers IDRIVEP, IDRIVEN, TDRIVEP, and TDRIVEN are set based on the gate charge of the external FETs used (Qg), and the desired rise time (RT). RT is the time it will take to charge the FET gate and turn on.

Equation 10. IDRIVE > Q / RT
Equation 11. TDRIVE > 2 × RT

IDRIVEN / IDRIVEP and TDRIVEN / TDRIVEP should be selected to be the smallest settings that meet the requirements in Equation 10 and Equation 11.

DRIVE Register Address = 0x06h
Bit Name Size R/W Default Description
5-4 TDRIVEN 2 R/W 01 Gate drive sink time
00: 250 ns
01: 500 ns
10: 1 µs
11: 2 µs
7-6 TDRIVEP 2 R/W 01 Gate drive source time
00: 250 ns
01: 500 ns
10: 1 µs
11: 2 µs
9-8 IDRIVEN 2 R/W 00 Gate drive peak sink current
00: 100 mA peak (sink)
01: 200 mA peak (sink)
10: 300 mA peak (sink)
11: 400 mA peak (sink)
11-10 IDRIVEP 2 R/W 00 Gate drive peak source current
00: 50 mA peak (source)
01: 100 mA peak (source)
10: 150 mA peak (source)
11: 200 mA peak (source)