SLVSEA2D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
Table 8-49 lists the DRV8718-Q1_CONTROL_ADV registers. All register offset addresses not listed in Table 8-49 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
2Ah | AGD_CTRL1 | Adaptive gate drive general control functions | Go |
2Bh | PDR_CTRL1 | Half-bridge 1 and 2 PDR delay and max current settings | Go |
2Ch | PDR_CTRL2 | Half-bridge 3 and 4 PDR delay and max current settings | Go |
2Dh | PDR_CTRL3 | Half-bridge 5 and 6 PDR delay and max current settings | Go |
2Eh | PDR_CTRL4 | Half-bridge 7 and 8 PDR delay and max current settings | Go |
2Fh | PDR_CTRL5 | Half-bridge 1 and 2 PDR charge and discharge initial settings. | Go |
30h | PDR_CTRL6 | Half-bridge 3 and 4 PDR charge and discharge initial settings. | Go |
31h | PDR_CTRL7 | Half-bridge 5 and 6 PDR charge and discharge initial settings. | Go |
32h | PDR_CTRL8 | Half-bridge 7 and 8 PDR charge and discharge initial settings. | Go |
33h | PDR_CTRL9 | Half-bridge 1-4 PDR loop controller gain | Go |
34h | PDR_CTRL10 | Half-bridge 5-8 PDR loop controller gain | Go |
35h | STC_CTRL1 | Half-bridge 1 and 2 STC rise/fall time and controller gain | Go |
36h | STC_CTRL2 | Half-bridge 3 and 4 STC rise/fall time and controller gain | Go |
37h | STC_CTRL3 | Half-bridge 5 and 6 STC rise/fall time and controller gain | Go |
38h | STC_CTRL4 | Half-bridge 7 and 8 STC rise/fall time and controller gain | Go |
39h | DCC_CTRL1 | Half-bridge 1-8 DCC enable and manual control | Go |
3Ah | PST_CTRL1 | Half-bridge 1-8 freewheel and post charge delay control | Go |
3Bh | PST_CTRL2 | Half-bridge 1-8 post charge controller gain | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-50 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
- n | Value after reset or the default value |
AGD_CTRL1 is shown in Figure 8-41 and described in Table 8-51.
Return to the Summary Table.
Control register for adaptive gate drive voltage thresholds, pull down setting, and active half-bridge configuration.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AGD_THR | AGD_ISTRONG | SET_AGD_12 | SET_AGD_34 | SET_AGD_56 | SET_AGD_78 | ||
R/W-01b | R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | AGD_THR | R/W | 01b | Adaptive gate driver VSH threshold configuration.
00b = 1V, VDRAIN - 0.5V 01b = 1V, VDRAIN - 1V 10b = 2V, VDRAIN - 1.5V 11b = 2V, VDRAIN - 2V |
5-4 | AGD_ISTRONG | R/W | 00b | Adaptive gate driver ISTRONG configuration.
00b = ISTRONG pulldown decoded from initial IDRVP_x register setting. 01b = 62 mA 10b = 124 mA 11b = RSVD |
3 | SET_AGD_12 | R/W | 0b | Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 1 1b = Half-bridge 2 |
2 | SET_AGD_34 | R/W | 0b | Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 3 1b = Half-bridge 4 |
1 | SET_AGD_56 | R/W | 0b | Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 5 1b = Half-bridge 6 |
0 | SET_AGD_78 | R/W | 0b | Set active half-bridge for adaptive gate drive control loops.
0b = Half-bridge 7 1b = Half-bridge 8 |
PDR_CTRL1 is shown in Figure 8-42 and described in Table 8-52.
Return to the Summary Table.
Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRE_MAX_12 | T_DON_DOFF_12 | ||||||
R/W-00b | R/W-001010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | PRE_MAX_12 | R/W | 00b | Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 1 and 2.
00b = 64 mA 01b = 32 mA 10b = 16 mA 11b = 8 mA |
5-0 | T_DON_DOFF_12 | R/W | 001010b | On and off time delay for half-bridge 1 and 2. 140 ns x T_DON_DOFF_12 [3:0] Default time: 001010b (1.4 us) |
PDR_CTRL2 is shown in Figure 8-43 and described in Table 8-53.
Return to the Summary Table.
Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 3 and 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRE_MAX_34 | T_DON_DOFF_34 | ||||||
R/W-00b | R/W-001010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | PRE_MAX_34 | R/W | 00b | Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 3 and 4.
00b = 64 mA 01b = 32 mA 10b = 16 mA 11b = 8 mA |
5-0 | T_DON_DOFF_34 | R/W | 001010b | On and off time delay for half-bridge 3 and 4. 140 ns x T_DON_DOFF_34 [3:0] Default time: 001010b (1.4 us) |
PDR_CTRL3 is shown in Figure 8-44 and described in Table 8-54.
Return to the Summary Table.
Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 5 and 6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRE_MAX_56 | T_DON_DOFF_56 | ||||||
R/W-00b | R/W-001010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | PRE_MAX_56 | R/W | 00b | Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 5 and 6.
00b = 64 mA 01b = 32 mA 10b = 16 mA 11b = 8 mA |
5-0 | T_DON_DOFF_56 | R/W | 001010b | On and off time delay for half-bridge 5 and 6. 140 ns x T_DON_DOFF_56 [3:0] Default time: 001010b (1.4 us) |
PDR_CTRL4 is shown in Figure 8-45 and described in Table 8-55.
Return to the Summary Table.
Control register for tON_OFF propagation delay and pre-charge/discharge max current for half-bridges 7 and 8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRE_MAX_78 | T_DON_DOFF_78 | ||||||
R/W-00b | R/W-001010b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | PRE_MAX_78 | R/W | 00b | Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 7 and 8.
00b = 64 mA 01b = 32 mA 10b = 16 mA 11b = 8 mA |
5-0 | T_DON_DOFF_78 | R/W | 001010b | On and off time delay for half-bridge 7 and 8. 140 ns x T_DON_DOFF_78 [3:0] Default time: 001010b (1.4 us) |
PDR_CTRL5 is shown in Figure 8-46 and described in Table 8-56.
Return to the Summary Table.
Control register for charge and pre-charge initial settings for half-bridges 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_PRE_CHR_12 | T_PRE_DCHR_12 | PRE_CHR_INIT_12 | PRE_DCHR_INIT_12 | ||||
R/W-11b | R/W-11b | R/W-01b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | T_PRE_CHR_12 | R/W | 11b | PDR control loop pre-charge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
5-4 | T_PRE_DCHR_12 | R/W | 11b | PDR control loop pre-discharge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
3-2 | PRE_CHR_INIT_12 | R/W | 01b | PDR control loop initial pre-charge current setting for half-bridge 1 and 2.
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
1-0 | PRE_DCHR_INIT_12 | R/W | 10b | PDR control loop initial pre-discharge current setting for half-bridge 1 and 2..
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
PDR_CTRL6 is shown in Figure 8-47 and described in Table 8-57.
Return to the Summary Table.
Control register for charge and pre-charge initial settings for half-bridges 3 and 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_PRE_CHR_34 | T_PRE_DCHR_34 | PRE_CHR_INIT_34 | PRE_DCHR_INIT_34 | ||||
R/W-11b | R/W-11b | R/W-01b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | T_PRE_CHR_34 | R/W | 11b | PDR control loop pre-charge time for half-bridge 3 and 4. Set as ratio of T_DON_DOFF_34 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
5-4 | T_PRE_DCHR_34 | R/W | 11b | PDR control loop pre-discharge time for half-bridge 3 and 4. Set as ratio of T_DON_DOFF_34 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
3-2 | PRE_CHR_INIT_34 | R/W | 01b | PDR control loop initial pre-charge current setting for half-bridge 3 and 4.
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
1-0 | PRE_DCHR_INIT_34 | R/W | 10b | PDR control loop initial pre-discharge current setting for half-bridge 3 and 4.
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
PDR_CTRL7 is shown in Figure 8-48 and described in Table 8-58.
Return to the Summary Table.
Control register for charge and pre-charge initial settings for half-bridges 5 and 6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_PRE_CHR_56 | T_PRE_DCHR_56 | PRE_CHR_INIT_56 | PRE_DCHR_INIT_56 | ||||
R/W-11b | R/W-11b | R/W-01b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | T_PRE_CHR_56 | R/W | 11b | PDR control loop pre-charge time for half-bridge 5 and 6. Set as ratio of T_DON_DOFF_56 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
5-4 | T_PRE_DCHR_56 | R/W | 11b | PDR control loop pre-discharge time for half-bridge 5 and 6. Set as ratio of T_DON_DOFF_56 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
3-2 | PRE_CHR_INIT_56 | R/W | 01b | PDR control loop initial pre-charge current setting for half-bridge 5 and 6.
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
1-0 | PRE_DCHR_INIT_56 | R/W | 10b | PDR control loop initial pre-discharge current setting for half-bridge 5 and 6.
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
PDR_CTRL8 is shown in Figure 8-49 and described in Table 8-59.
Return to the Summary Table.
Control register for charge and pre-charge initial settings for half-bridges 7 and 8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_PRE_CHR_78 | T_PRE_DCHR_78 | PRE_CHR_INIT_78 | PRE_DCHR_INIT_78 | ||||
R/W-11b | R/W-11b | R/W-01b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | T_PRE_CHR_78 | R/W | 11b | PDR control loop pre-charge time for half-bridge 7 and 8. Set as ratio of T_DON_DOFF_78 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
5-4 | T_PRE_DCHR_78 | R/W | 11b | PDR control loop pre-discharge time for half-bridge 7 and 8. Set as ratio of T_DON_DOFF_78 [5:0]
00b = 1/8 01b = 1/4 10b = 3/8 11b = 1/2 |
3-2 | PRE_CHR_INIT_78 | R/W | 01b | PDR control loop initial pre-charge current setting for half-bridge 7 and 8.
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
1-0 | PRE_DCHR_INIT_78 | R/W | 10b | PDR control loop initial pre-discharge current setting for half-bridge 7 and 8.
00b = 4 mA 01b = 8 mA 10b = 16 mA 11b = 32 mA |
PDR_CTRL9 is shown in Figure 8-50 and described in Table 8-60.
Return to the Summary Table.
Control register to configure PDR Kp loop controller gain setting for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_PDR_12 | PDR_ERR_12 | KP_PDR_12 | EN_PDR_34 | PDR_ERR_34 | KP_PDR_34 | ||
R/W-0b | R/W-0b | R/W-01b | R/W-0b | R/W-0b | R/W-01b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_PDR_12 | R/W | 0b | Enable PDR loop control for half-bridge 1 and 2. |
6 | PDR_ERR_12 | R/W | 0b | PDR loop error limit for half-bridge 1 and 2.
0b = 1-bit error 1b = Actual error |
5-4 | KP_PDR_12 | R/W | 01b | PDR proportional controller gain setting for half-bridge 1 and 2.
00b = 1 01b = 2 10b = 3 11b = 4 |
3 | EN_PDR_34 | R/W | 0b | Enable PDR loop control for half-bridge 3 and 4. |
2 | PDR_ERR_34 | R/W | 0b | PDR loop error limit for half-bridge 3 and 4.
0b = 1-bit error 1b = Actual error |
1-0 | KP_PDR_34 | R/W | 01b | PDR proportional controller gain setting for half-bridge 3 and 4.
00b = 1 01b = 2 10b = 3 11b = 4 |
PDR_CTRL10 is shown in Figure 8-51 and described in Table 8-61.
Return to the Summary Table.
Control register to configure PDR Kp loop controller gain setting for half-bridges 5-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_PDR_56 | PDR_ERR_56 | KP_PDR_56 | EN_PDR_78 | PDR_ERR_78 | KP_PDR_78 | ||
R/W-0b | R/W-0b | R/W-01b | R/W-0b | R/W-0b | R/W-01b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_PDR_56 | R/W | 0b | Enable PDR loop control for half-bridge 5 and 6. |
6 | PDR_ERR_56 | R/W | 0b | PDR loop error limit for half-bridge 5 and 6.
0b = 1-bit error 1b = Actual error |
5-4 | KP_PDR_56 | R/W | 01b | PDR proportional controller gain setting for half-bridge 5 and 6.
00b = 1 01b = 2 10b = 3 11b = 4 |
3 | EN_PDR_78 | R/W | 0b | Enable PDR loop control for half-bridge 7 and 8. |
2 | PDR_ERR_78 | R/W | 0b | PDR loop error limit for half-bridge 7 and 8.
0b = 1-bit error 1b = Actual error |
1-0 | KP_PDR_78 | R/W | 01b | PDR proportional controller gain setting for half-bridge 7 and 8.
00b = 1 01b = 2 10b = 3 11b = 4 |
STC_CTRL1 is shown in Figure 8-52 and described in Table 8-62.
Return to the Summary Table.
Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_RISE_FALL_12 | EN_STC_12 | STC_ERR_12 | KP_STC_12 | ||||
R/W-0010b | R/W-0b | R/W-0b | R/W-11b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | T_RISE_FALL_12 | R/W | 0010b | Set switch-node VSH rise and fall time for half-bridge 1 and 2.
0000b = 0.35 us 0001b = 0.56 us 0010b = 0.77 us 0011b = 0.98 us 0100b = 1.33 us 0101b = 1.68 us 0110b = 2.03 us 0111b = 2.45 us 1000b = 2.94 us 1001b = 3.99 us 1010b = 4.97 us 1011b = 5.95 us 1100b = 7.98 us 1101b = 9.94 us 1110b = 11.97 us 1111b = 15.96 us |
3 | EN_STC_12 | R/W | 0b | Enable STC loop control for half-bridge 1 and 2. |
2 | STC_ERR_12 | R/W | 0b | STC loop error limit for half-bridge 1 and 2
0b = 1-bit error 1b = Actual error |
1-0 | KP_STC_12 | R/W | 11b | STC proportional controller gain setting for half-bridge 1 and 2.
00b = 1 01b = 2 10b = 3 11b = 4 |
STC_CTRL2 is shown in Figure 8-53 and described in Table 8-63.
Return to the Summary Table.
Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 3 and 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_RISE_FALL_34 | EN_STC_34 | STC_ERR_34 | KP_STC_34 | ||||
R/W-0010b | R/W-0b | R/W-0b | R/W-11b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | T_RISE_FALL_34 | R/W | 0010b | Set switch-node VSH rise and fall time for half-bridge 3 and 4.
0000b = 0.35 us 0001b = 0.56 us 0010b = 0.77 us 0011b = 0.98 us 0100b = 1.33 us 0101b = 1.68 us 0110b = 2.03 us 0111b = 2.45 us 1000b = 2.94 us 1001b = 3.99 us 1010b = 4.97 us 1011b = 5.95 us 1100b = 7.98 us 1101b = 9.94 us 1110b = 11.97 us 1111b = 15.96 us |
3 | EN_STC_34 | R/W | 0b | Enable STC loop control for half-bridge 3 and 4. |
2 | STC_ERR_34 | R/W | 0b | STC loop error limit for half-bridge 3 and 4.
0b = 1-bit error 1b = Actual error |
1-0 | KP_STC_34 | R/W | 11b | STC proportional controller gain setting for half-bridge 3 and 4.
00b = 1 01b = 2 10b = 3 11b = 4 |
STC_CTRL3 is shown in Figure 8-54 and described in Table 8-64.
Return to the Summary Table.
Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 5 and 6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_RISE_FALL_56 | EN_STC_56 | STC_ERR_56 | KP_STC_56 | ||||
R/W-0010b | R/W-0b | R/W-0b | R/W-11b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | T_RISE_FALL_56 | R/W | 0010b | Set switch-node VSH rise and fall time for half-bridge 5 and 6.
0000b = 0.35 us 0001b = 0.56 us 0010b = 0.77 us 0011b = 0.98 us 0100b = 1.33 us 0101b = 1.68 us 0110b = 2.03 us 0111b = 2.45 us 1000b = 2.94 us 1001b = 3.99 us 1010b = 4.97 us 1011b = 5.95 us 1100b = 7.98 us 1101b = 9.94 us 1110b = 11.97 us 1111b = 15.96 us |
3 | EN_STC_56 | R/W | 0b | Enable STC loop control for half-bridge 5 and 6. |
2 | STC_ERR_56 | R/W | 0b | STC loop error limit for half-bridge 5 and 6.
0b = 1-bit error 1b = Actual error |
1-0 | KP_STC_56 | R/W | 11b | STC proportional controller gain setting for half-bridge 5 and 6.
00b = 1 01b = 2 10b = 3 11b = 4 |
STC_CTRL4 is shown in Figure 8-55 and described in Table 8-65.
Return to the Summary Table.
Control register to configure STC rise/fall time and Kp loop controller gain setting for half-bridges 7 and 8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
T_RISE_FALL_78 | EN_STC_78 | STC_ERR_78 | KP_STC_78 | ||||
R/W-0010b | R/W-0b | R/W-0b | R/W-11b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | T_RISE_FALL_78 | R/W | 0010b | Set switch-node VSH rise and fall time for half-bridge 7 and 8.
0000b = 0.35 us 0001b = 0.56 us 0010b = 0.77 us 0011b = 0.98 us 0100b = 1.33 us 0101b = 1.68 us 0110b = 2.03 us 0111b = 2.45 us 1000b = 2.94 us 1001b = 3.99 us 1010b = 4.97 us 1011b = 5.95 us 1100b = 7.98 us 1101b = 9.94 us 1110b = 11.97 us 1111b = 15.96 us |
3 | EN_STC_78 | R/W | 0b | Enable STC loop control for half-bridge 7 and 8. |
2 | STC_ERR_78 | R/W | 0b | STC loop error limit for half-bridge 7 and 8.
0b = 1-bit error 1b = Actual error |
1-0 | KP_STC_78 | R/W | 11b | STC proportional controller gain setting for half-bridge 7 and 8.
00b = 1 01b = 2 10b = 3 11b = 4 |
DCC_CTRL1 is shown in Figure 8-56 and described in Table 8-66.
Return to the Summary Table.
Control register to enable DCC loop and manual configuration for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_DCC_12 | EN_DCC_34 | EN_DCC_56 | EN_DCC_78 | IDIR_MAN_12 | IDIR_MAN_34 | IDIR_MAN_56 | IDIR_MAN_78 |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_DCC_12 | R/W | 0b | Enable duty cycle compensation for half-bridge 1 and 2. |
6 | EN_DCC_34 | R/W | 0b | Enable duty cycle compensation for half-bridge 3 and 4. |
5 | EN_DCC_56 | R/W | 0b | Enable duty cycle compensation for half-bridge 5 and 6. |
4 | EN_DCC_78 | R/W | 0b | Enable duty cycle compensation for half-bridge 7 and 8. |
3 | IDIR_MAN_12 | R/W | 0b | Current polarity detection mode for half-bridge 1 and 2.
0b = Automatic 1b = Manual (Set by HBx_HL) |
2 | IDIR_MAN_34 | R/W | 0b | Current polarity detection mode for half-bridge 3 and 4.
0b = Automatic 1b = Manual (Set by HBx_HL) |
1 | IDIR_MAN_56 | R/W | 0b | Current polarity detection mode for half-bridge 5 and 6.
0b = Automatic 1b = Manual (Set by HBx_HL) |
0 | IDIR_MAN_78 | R/W | 0b | Current polarity detection mode for half-bridge 7 and 8.
0b = Automatic 1b = Manual (Set by HBx_HL) |
PST_CTRL1 is shown in Figure 8-57 and described in Table 8-67.
Return to the Summary Table.
Control register to configure max freewheeling current and post charge delay for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FW_MAX_12 | FW_MAX_34 | FW_MAX_56 | FW_MAX_78 | EN_PST_DLY_12 | EN_PST_DLY_34 | EN_PST_DLY_56 | EN_PST_DLY_78 |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-1b | R/W-1b | R/W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FW_MAX_12 | R/W | 0b | Gate drive current used for freewheeling MOSFET for half-bridge 1 and 2.
0b = PRE_CHR_MAX_12 [1:0] 1b = 64 mA |
6 | FW_MAX_34 | R/W | 0b | Gate drive current used for freewheeling MOSFET for half-bridge 3 and 4.
0b = PRE_CHR_MAX_34 [1:0] 1b = 64 mA |
5 | FW_MAX_56 | R/W | 0b | Gate drive current used for freewheeling MOSFET for half-bridge 5 and 6.
0b = PRE_CHR_MAX_56 [1:0] 1b = 64 mA |
4 | FW_MAX_78 | R/W | 0b | Gate drive current used for freewheeling MOSFET for half-bridge 7 and 8.
0b = PRE_CHR_MAX_78 [1:0] 1b = 64 mA |
3 | EN_PST_DLY_12 | R/W | 1b | Enable post-charge time delay. Time delay is equal to T_DON_DOFF_12 - T_PRE_CHR_12. |
2 | EN_PST_DLY_34 | R/W | 1b | Enable post-charge time delay. Time delay is equal to T_DON_DOFF_34 - T_PRE_CHR_34. |
1 | EN_PST_DLY_56 | R/W | 1b | Enable post-charge time delay. Time delay is equal to T_DON_DOFF_56 - T_PRE_CHR_56. |
0 | EN_PST_DLY_78 | R/W | 1b | Enable post-charge time delay. Time delay is equal to T_DON_DOFF_78 - T_PRE_CHR_78. |
PST_CTRL2 is shown in Figure 8-58 and described in Table 8-68.
Return to the Summary Table.
Control register to configure post charge Kp loop controller gain setting for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KP_PST_12 | KP_PST_34 | KP_PST_56 | KP_PST_78 | ||||
R/W-01b | R/W-01b | R/W-01b | R/W-01b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | KP_PST_12 | R/W | 01b | Post charge proportional control gain setting for half-bridges 1 and 2.
00b = Disabled 01b = 2 10b = 4 11b = 15 |
5-4 | KP_PST_34 | R/W | 01b | Post charge proportional control gain setting for half-bridges 3 and 4.
00b = Disabled 01b = 2 10b = 4 11b = 15 |
3-2 | KP_PST_56 | R/W | 01b | Post charge proportional control gain setting for half-bridges 5 and 6.
00b = Disabled 01b = 2 10b = 4 11b = 15 |
1-0 | KP_PST_78 | R/W | 01b | Post charge proportional control gain setting for half-bridges 7 and 8.
00b = Disabled 01b = 2 10b = 4 11b = 15 |