SLVSEA2D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
Table 8-14 lists the DRV8718-Q1_CONTROL registers. All register offset addresses not listed in Table 8-14 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
7h | IC_CTRL1 | Device general function control register 1 | Go |
8h | IC_CTRL2 | Device general function control register 2 | Go |
9h | BRG_CTRL1 | Half-bridge 1-4 output state control | Go |
Ah | BRG_CTRL2 | Half-bridge 5-8 output state control | Go |
Bh | PWM_CTRL1 | Half-bridge 1-4 PWM mapping control | Go |
Ch | PWM_CTRL2 | Half-bridge 5-8 PWM mapping control | Go |
Dh | PWM_CTRL3 | Half-bridge 1-8 high-side or low-side drive control | Go |
Eh | PWM_CTRL4 | Half-bridge 1-8 freewheeling configuration | Go |
Fh | IDRV_CTRL1 | Half-bridge 1 gate drive source/sink current | Go |
10h | IDRV_CTRL2 | Half-bridge 2 gate drive source/sink current | Go |
11h | IDRV_CTRL3 | Half-bridge 3 gate drive source/sink current | Go |
12h | IDRV_CTRL4 | Half-bridge 4 gate drive source/sink current | Go |
13h | IDRV_CTRL5 | Half-bridge 5 gate drive source/sink current | Go |
14h | IDRV_CTRL6 | Half-bridge 6 gate drive source/sink current | Go |
15h | IDRV_CTRL7 | Half-bridge 7 gate drive source/sink current | Go |
16h | IDRV_CTRL8 | Half-bridge 8 gate drive source/sink current | Go |
17h | IDRV_CTRL9 | Half-bridge 1-8 gate drive low current control | Go |
18h | DRV_CTRL1 | Gate driver VGS and VDS monitor configuration | Go |
19h | DRV_CTRL2 | Half-bridge 1-4 VGS and VDS tDRV configuration | Go |
1Ah | DRV_CTRL3 | Half-bridge 5-8 VGS and VDS tDRV configuration | Go |
1Bh | DRV_CTRL4 | Half-bridge 1-8 VGS tDEAD_D configuration | Go |
1Ch | DRV_CTRL5 | Half-bridge 1-8 VDS tDS_DG configuration | Go |
1Dh | DRV_CTRL6 | Half-bridge 1-8 VDS fault pulldown current configuration | Go |
1Fh | VDS_CTRL1 | Half-bridge 1 and 2 VDS overcurrent threshold | Go |
20h | VDS_CTRL2 | Half-bridge 3 and 4 VDS overcurrent threshold | Go |
21h | VDS_CTRL3 | Half-bridge 5 and 6 VDS overcurrent threshold | Go |
22h | VDS_CTRL4 | Half-bridge 7 and 8 VDS overcurrent threshold | Go |
23h | OLSC_CTRL1 | Half-bridge 1-4 offline diagnostic control | Go |
24h | OLSC_CTRL2 | Half-bridge 5-8 offline diagnostic control | Go |
25h | UVOV_CTRL | Undervoltage and overvoltage monitor configuration. | Go |
26h | CSA_CTRL1 | Shunt amplifier 1 and 2 configuration | Go |
27h | CSA_CTRL2 | Shunt amplifier 1 blanking configuration | Go |
28h | CSA_CTRL3 | Shunt amplifier 2 blanking configuration | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-15 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
- n | Value after reset or the default value |
IC_CTRL1 is shown in Figure 8-8 and described in Table 8-16.
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Control register for driver and diagnostic enable, SPI lock, and clear fault command.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_DRV | EN_OLSC | RESERVED | LOCK | CLR_FLT | |||
R/W-0b | R/W-0b | R-00b | R/W-011b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_DRV | R/W | 0b | Enable gate drivers.
0b = Gate driver output disabled and passive pulldowns enabled. 1b = Gate driver outputs enabled. |
6 | EN_OLSC | R/W | 0b | Enable offline open load and short circuit diagnostic.
0b = Disabled. 1b = VDS monitors set into real-time voltage monitor mode and offline diagnostics current sources enabled. |
5-4 | RESERVED | R | 00b | Reserved |
3-1 | LOCK | R/W | 011b | Lock and unlock the control registers. Bit settings not listed have no effect.
011b = Unlock all control registers. 110b = Lock the control registers by ignoring further writes except to the LOCK register. |
0 | CLR_FLT | R/W | 0b | Clear latched fault status information.
0b = Default state. 1b = Clear latched fault bits, resets to 0b after completion. Will also clear SPI fault and watchdog fault status. |
IC_CTRL2 is shown in Figure 8-9 and described in Table 8-17.
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Control register for pin mode, charge pump mode, and watchdog.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_SSC | DRVOFF_nFLT | CP_MODE | WD_EN | WD_FLT_M | WD_WIN | WD_RST | |
R/W-0b | R/W-0b | R/W-00b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIS_SSC | R/W | 0b | Spread spectrum clocking
0b = Enabled. 1b = Disabled. |
6 | DRVOFF_nFLT | R/W | 0b | Sets DRVOFF/nFLT multi-function pin mode.
0b = Pin functions as DRVOFF global driver disable. 1b = Pin functions as nFLT open-drain fault interrupt output. |
5-4 | CP_MODE | R/W | 00b | Charge pump operating mode.
00b = Automatic switch between tripler and doubler mode. 01b = Always doubler mode. 10b = Always tripler mode. 11b = RSVD |
3 | WD_EN | R/W | 0b | Watchdog timer enable.
0b = Watchdog timer disabled. 1b = Watchdog dog timer enabled. |
2 | WD_FLT_M | R/W | 0b | Watchdog fault mode. Watchdog fault is cleared by CLR_FLT.
0b = Watchdog fault is reported to WD_FLT and WARN register bits. Gate drivers remain enabled and nFAULT is not asserted. 1b = Watchdog fault is reported to WD_FLT, FAULT register bits, and nFAULT pin. Gate drivers are disabled in response to watchdog fault. |
1 | WD_WIN | R/W | 1b | Watchdog timer window.
0b = 4 to 40 ms 1b = 10 to 100 ms |
0 | WD_RST | R/W | 0b | Watchdog restart. 0b by default after power up. Invert this bit to restart the watchdog timer. After written, the bit will reflect the new inverted value. |
BRG_CTRL1 is shown in Figure 8-10 and described in Table 8-18.
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Control register to set the output state for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_CTRL | HB2_CTRL | HB3_CTRL | HB4_CTRL | ||||
R/W-00b | R/W-00b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HB1_CTRL | R/W | 00b | Half-bridge 1 output state control.
00b = High impedance (HI-Z). GH1 and GL1 pulldown. 01b = Drive low-side (LO). GH1 pulldown and GL1 pullup. 10b = Drive high-side (HI). GH1 pullup and GL1 pulldown. 11b = Input PWM control. HB1_PWM, HB1_HL, and HB1_FW. |
5-4 | HB2_CTRL | R/W | 00b | Half-bridge 2 output state control.
00b = High impedance (HI-Z). GH2 and GL2 pulldown. 01b = Drive low-side (LO). GH2 pulldown and GL2 pullup. 10b = Drive high-side (HI). GH2 pullup and GL2 pulldown. 11b = Input PWM control. HB2_PWM, HB2_HL, and HB2_FW. |
3-2 | HB3_CTRL | R/W | 00b | Half-bridge 3 output state control.
00b = High impedance (HI-Z). GH3 and GL3 pulldown. 01b = Drive low-side (LO). GH3 pulldown and GL3 pullup. 10b = Drive high-side (HI). GH3 pullup and GL3 pulldown. 11b = Input PWM control. HB3_PWM, HB3_HL, and HB3_FW. |
1-0 | HB4_CTRL | R/W | 00b | Half-bridge 4 output state control.
00b = High impedance (HI-Z). GH4 and GL4 pulldown. 01b = Drive low-side (LO). GH4 pulldown and GL4 pullup. 10b = Drive high-side (HI). GH4 pullup and GL4 pulldown. 11b = Input PWM control. HB4_PWM, HB4_HL, and HB4_FW. |
BRG_CTRL2 is shown in Figure 8-11 and described in Table 8-19.
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Control register to set the output state for half-bridges 5-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB5_CTRL | HB6_CTRL | HB7_CTRL | HB8_CTRL | ||||
R/W-00b | R/W-00b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HB5_CTRL | R/W | 00b | Half-bridge 5 output state control.
00b = High impedance (HI-Z). GH5 and GL5 pulldown. 01b = Drive low-side (LO). GH5 pulldown and GL5 pullup. 10b = Drive high-side (HI). GH5 pullup and GL5 pulldown. 11b = Input PWM control. HB5_PWM, HB5_HL, and HB5_FW. |
5-4 | HB6_CTRL | R/W | 00b | Half-bridge 6 output state control.
00b = High impedance (HI-Z). GH6 and GL6 pulldown. 01b = Drive low-side (LO). GH6 pulldown and GL6 pullup. 10b = Drive high-side (HI). GH6 pullup and GL6 pulldown. 11b = Input PWM control. HB6_PWM, HB6_HL, and HB6_FW. |
3-2 | HB7_CTRL | R/W | 00b | Half-bridge 7 output state control.
00b = High impedance (HI-Z). GH7 and GL7 pulldown. 01b = Drive low-side (LO). GH7 pulldown and GL7 pullup. 10b = Drive high-side (HI). GH7 pullup and GL7 pulldown. 11b = Input PWM control. HB7_PWM, HB7_HL, and HB7_FW. |
1-0 | HB8_CTRL | R/W | 00b | Half-bridge 8 output state control.
00b = High impedance (HI-Z). GH8 and GL8 pulldown. 01b = Drive low-side (LO). GH8 pulldown and GL8 pullup. 10b = Drive high-side (HI). GH8 pullup and GL8 pulldown. 11b = Input PWM control. HB8_PWM, HB8_HL, and HB8_FW. |
PWM_CTRL1 is shown in Figure 8-12 and described in Table 8-20.
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Control register to map the input PWM source for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_PWM | HB2_PWM | HB3_PWM | HB4_PWM | ||||
R/W-00b | R/W-00b | R/W-01b | R/W-01b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HB1_PWM | R/W | 00b | Configure PWM input source for half-bridge 1.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
5-4 | HB2_PWM | R/W | 00b | Configure PWM input source for half-bridge 2.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
3-2 | HB3_PWM | R/W | 01b | Configure PWM input source for half-bridge 3.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
1-0 | HB4_PWM | R/W | 01b | Configure PWM input source for half-bridge 4.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
PWM_CTRL2 is shown in Figure 8-13 and described in Table 8-21.
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Control register to map the input PWM source for half-bridges 5-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB5_PWM | HB6_PWM | HB7_PWM | HB8_PWM | ||||
R/W-10b | R/W-10b | R/W-11b | R/W-11b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HB5_PWM | R/W | 10b | Configure PWM input source for half-bridge 5.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
5-4 | HB6_PWM | R/W | 10b | Configure PWM input source for half-bridge 6.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
3-2 | HB7_PWM | R/W | 11b | Configure PWM input source for half-bridge 7.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
1-0 | HB8_PWM | R/W | 11b | Configure PWM input source for half-bridge 8.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
PWM_CTRL3 is shown in Figure 8-14 and described in Table 8-22.
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Control register to set the PWM drive MOSFET (high or low) for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_HL | HB2_HL | HB3_HL | HB4_HL | HB5_HL | HB6_HL | HB7_HL | HB8_HL |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | HB1_HL | R/W | 0b | Set half-bridge 1 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
6 | HB2_HL | R/W | 0b | Set half-bridge 2 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
5 | HB3_HL | R/W | 0b | Set half-bridge 3 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
4 | HB4_HL | R/W | 0b | Set half-bridge 4 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
3 | HB5_HL | R/W | 0b | Set half-bridge 5 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
2 | HB6_HL | R/W | 0b | Set half-bridge 6 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
1 | HB7_HL | R/W | 0b | Set half-bridge 7 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
0 | HB8_HL | R/W | 0b | Set half-bridge 8 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
PWM_CTRL4 is shown in Figure 8-15 and described in Table 8-23.
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Control register to set the PWM freewheeling mode for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_FW | HB2_FW | HB3_FW | HB4_FW | HB5_FW | HB6_FW | HB7_FW | HB8_FW |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | HB1_FW | R/W | 0b | Configure freewheeling setting for half-bridge 1.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
6 | HB2_FW | R/W | 0b | Configure freewheeling setting for half-bridge 2.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
5 | HB3_FW | R/W | 0b | Configure freewheeling setting for half-bridge 3.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
4 | HB4_FW | R/W | 0b | Configure freewheeling setting for half-bridge 4.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
3 | HB5_FW | R/W | 0b | Configure freewheeling setting for half-bridge 5.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
2 | HB6_FW | R/W | 0b | Configure freewheeling setting for half-bridge 6.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
1 | HB7_FW | R/W | 0b | Configure freewheeling setting for half-bridge 7.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
0 | HB8_FW | R/W | 0b | Configure freewheeling setting for half-bridge 8.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
IDRV_CTRL1 is shown in Figure 8-16 and described in Table 8-24.
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Control register to configure the source and sink current for the half-bridge 1 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_1 | IDRVN_1 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_1 | R/W | 1111b | Half-bridge 1 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO1).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_1 | R/W | 1111b | Half-bridge 1 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO1).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL2 is shown in Figure 8-17 and described in Table 8-25.
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Control register to configure the source and sink current for the half-bridge 2 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_2 | IDRVN_2 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_2 | R/W | 1111b | Half-bridge 2 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO2).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_2 | R/W | 1111b | Half-bridge 2 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO2).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL3 is shown in Figure 8-18 and described in Table 8-26.
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Control register to configure the source and sink current for the half-bridge 3 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_3 | IDRVN_3 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_3 | R/W | 1111b | Half-bridge 3 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO3).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_3 | R/W | 1111b | Half-bridge 3 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO3).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL4 is shown in Figure 8-19 and described in Table 8-27.
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Control register to configure the source and sink current for the half-bridge 4 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_4 | IDRVN_4 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_4 | R/W | 1111b | Half-bridge 4 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO4).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_4 | R/W | 1111b | Half-bridge 4 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO4).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL5 is shown in Figure 8-20 and described in Table 8-28.
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Control register to configure the source and sink current for the half-bridge 5 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_5 | IDRVN_5 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_5 | R/W | 1111b | Half-bridge 5 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO5).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_5 | R/W | 1111b | Half-bridge 5 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO5).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL6 is shown in Figure 8-21 and described in Table 8-29.
Return to the Summary Table.
Control register to configure the source and sink current for the half-bridge 6 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_6 | IDRVN_6 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_6 | R/W | 1111b | Half-bridge 6 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO6).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_6 | R/W | 1111b | Half-bridge 6 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO6).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL7 is shown in Figure 8-22 and described in Table 8-30.
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Control register to configure the source and sink current for the half-bridge 7 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_7 | IDRVN_7 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_7 | R/W | 1111b | Half-bridge 7 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO7).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_7 | R/W | 1111b | Half-bridge 7 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO7).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL8 is shown in Figure 8-23 and described in Table 8-31.
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Control register to configure the source and sink current for the half-bridge 8 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_8 | IDRVN_8 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_8 | R/W | 1111b | Half-bridge 8 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO8).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_8 | R/W | 1111b | Half-bridge 8 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO8).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL9 is shown in Figure 8-24 and described in Table 8-32.
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Control register to enable ultra-low source and sink current settings for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRV_LO1 | IDRV_LO2 | IDRV_LO3 | IDRV_LO4 | IDRV_LO5 | IDRV_LO6 | IDRV_LO7 | IDRV_LO8 |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IDRV_LO1 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 1.
0b = IDRVP_1 and IDRVN_1 utilize standard values. 1b = IDRVP_1 and IDRVN_1 utilize low current values. |
6 | IDRV_LO2 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 2.
0b = IDRVP_2 and IDRVN_2 utilize standard values. 1b = IDRVP_2 and IDRVN_2 utilize low current values. |
5 | IDRV_LO3 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 3.
0b = IDRVP_3 and IDRVN_3 utilize standard values. 1b = IDRVP_3 and IDRVN_3 utilize low current values. |
4 | IDRV_LO4 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 4.
0b = IDRVP_4 and IDRVN_4 utilize standard values. 1b = IDRVP_4 and IDRVN_4 utilize low current values. |
3 | IDRV_LO5 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 5.
0b = IDRVP_5 and IDRVN_5 utilize standard values. 1b = IDRVP_5 and IDRVN_5 utilize low current values. |
2 | IDRV_LO6 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 6.
0b = IDRVP_6 and IDRVN_6 utilize standard values. 1b = IDRVP_6 and IDRVN_6 utilize low current values. |
1 | IDRV_LO7 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 7.
0b = IDRVP_7 and IDRVN_7 utilize standard values. 1b = IDRVP_7 and IDRVN_7 utilize low current values. |
0 | IDRV_LO8 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 8.
0b = IDRVP_8 and IDRVN_8 utilize standard values. 1b = IDRVP_8 and IDRVN_8 utilize low current values. |
DRV_CTRL1 is shown in Figure 8-25 and described in Table 8-33.
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Control register to set the VGS and VDS monitor operating modes and configurations.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VGS_MODE | VGS_IND | VGS_LVL | VGS_HS_DIS | VDS_MODE | VDS_IND | ||
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-00b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VGS_MODE | R/W | 00b | VGS gate fault monitor mode for half-bridges 1-8.
00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled. |
5 | VGS_IND | R/W | 0b | VGS fault independent shutdown mode configuration.
0b = Disabled. VGS fault will shut down all half-bridge drivers. 1b = Enabled. VGS gate fault will only shutdown the associated half-bridge driver. |
4 | VGS_LVL | R/W | 0b | VGS threshold comparator level for dead-time handshake and VGS fault monitor for half-bridge drivers.
0b = 1.4 V 1b = 1 V |
3 | VGS_HS_DIS | R/W | 0b | VGS dead-time handshake monitor disable.
0b = 0x0 1b = Disabled. Half-bridge transition is based only on TDRIVE and programmable digital dead-time delays. |
2-1 | VDS_MODE | R/W | 00b | VDS overcurrent monitor mode for half-bridges 1-8.
00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled. |
0 | VDS_IND | R/W | 0b | VDS fault independent shutdown mode configuration.
0b = Disabled. VDS fault will shut down all half-bridge drivers. 1b = Enabled. VDS gate fault will only shutdown the associated half-bridge driver. |
DRV_CTRL2 is shown in Figure 8-26 and described in Table 8-34.
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Control register to set tDRV, the VGS drive and VDS monitor blanking time for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VGS_TDRV_12 | VGS_TDRV_34 | |||||
R-00b | R/W-010b | R/W-010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | VGS_TDRV_12 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 1 and 2.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
2-0 | VGS_TDRV_34 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 3 and 4.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
DRV_CTRL3 is shown in Figure 8-27 and described in Table 8-35.
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Control register to set tDRV, the VGS drive and VDS monitor blanking time for half-bridges 5-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VGS_TDRV_56 | VGS_TDRV_78 | |||||
R-00b | R/W-010b | R/W-010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | VGS_TDRV_56 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 5 and 6.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
2-0 | VGS_TDRV_78 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 7 and 8.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
DRV_CTRL4 is shown in Figure 8-28 and described in Table 8-36.
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Control register to set VGS tDEAD_D, additional digital dead-time insertion for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VGS_TDEAD_12 | VGS_TDEAD_34 | VGS_TDEAD_56 | VGS_TDEAD_78 | ||||
R/W-00b | R/W-00b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VGS_TDEAD_12 | R/W | 00b | Insertable digital dead-time for half-bridge 1 and 2.
00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
5-4 | VGS_TDEAD_34 | R/W | 00b | Insertable digital dead-time for half-bridge 3 and 4.
00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
3-2 | VGS_TDEAD_56 | R/W | 00b | Insertable digital dead-time for half-bridge 5 and 6.
00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
1-0 | VGS_TDEAD_78 | R/W | 00b | Insertable digital dead-time for half-bridge 7 and 8.
00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
DRV_CTRL5 is shown in Figure 8-29 and described in Table 8-37.
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Control register to set VDS tDS_DG, overcurrent monitor deglitch time for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_DG_12 | VDS_DG_34 | VDS_DG_56 | VDS_DG_78 | ||||
R/W-10b | R/W-10b | R/W-10b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VDS_DG_12 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 1 and 2.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
5-4 | VDS_DG_34 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 3 and 4.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
3-2 | VDS_DG_56 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 5 and 6.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
1-0 | VDS_DG_78 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 7 and 8.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
DRV_CTRL6 is shown in Figure 8-30 and described in Table 8-38.
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Control register to set the gate pulldown current (IDRVN) in response to VDS overcurrent fault for half-bridges 1-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_IDRVN_12 | VDS_IDRVN_34 | VDS_IDRVN_56 | VDS_IDRVN_78 | ||||
R/W-00b | R/W-00b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VDS_IDRVN_12 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 1 and 2.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
5-4 | VDS_IDRVN_34 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 3 and 4.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
3-2 | VDS_IDRVN_56 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 5 and 6.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
1-0 | VDS_IDRVN_78 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 7 and 8.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
VDS_CTRL1 is shown in Figure 8-31 and described in Table 8-39.
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Control register to set the VDS overcurrent monitor voltage threshold for half-bridges 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_LVL_1 | VDS_LVL_2 | ||||||
R/W-1101b | R/W-1101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | VDS_LVL_1 | R/W | 1101b | Half-bridge 1 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
3-0 | VDS_LVL_2 | R/W | 1101b | Half-bridge 2 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
VDS_CTRL2 is shown in Figure 8-32 and described in Table 8-40.
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Control register to set the VDS overcurrent monitor voltage threshold for half-bridges 3 and 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_LVL_3 | VDS_LVL_4 | ||||||
R/W-1101b | R/W-1101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | VDS_LVL_3 | R/W | 1101b | Half-bridge 3 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
3-0 | VDS_LVL_4 | R/W | 1101b | Half-bridge 4 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
VDS_CTRL3 is shown in Figure 8-33 and described in Table 8-41.
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Control register to set the VDS overcurrent monitor voltage threshold for half-bridges 5 and 6.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_LVL_5 | VDS_LVL_6 | ||||||
R/W-1101b | R/W-1101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | VDS_LVL_5 | R/W | 1101b | Half-bridge 5 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
3-0 | VDS_LVL_6 | R/W | 1101b | Half-bridge 6 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
VDS_CTRL4 is shown in Figure 8-34 and described in Table 8-42.
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Control register to set the VDS overcurrent monitor voltage threshold for half-bridges 7 and 8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_LVL_7 | VDS_LVL_8 | ||||||
R/W-1101b | R/W-1101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | VDS_LVL_7 | R/W | 1101b | Half-bridge 7 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
3-0 | VDS_LVL_8 | R/W | 1101b | Half-bridge 8 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
OLSC_CTRL1 is shown in Figure 8-35 and described in Table 8-43.
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Control register to enable and disable the offline diagnostic current sources for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PU_SH1 | PD_SH1 | PU_SH2 | PD_SH2 | PU_SH3 | PD_SH3 | PU_SH4 | PD_SH4 |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PU_SH1 | R/W | 0b | Half-bridge 1 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
6 | PD_SH1 | R/W | 0b | Half-bridge 1 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
5 | PU_SH2 | R/W | 0b | Half-bridge 2 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
4 | PD_SH2 | R/W | 0b | Half-bridge 2 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
3 | PU_SH3 | R/W | 0b | Half-bridge 3 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
2 | PD_SH3 | R/W | 0b | Half-bridge 3 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
1 | PU_SH4 | R/W | 0b | Half-bridge 4 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
0 | PD_SH4 | R/W | 0b | Half-bridge 4 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
OLSC_CTRL2 is shown in Figure 8-36 and described in Table 8-44.
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Control register to enable and disable the offline diagnostic current sources for half-bridges 5-8.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PU_SH5 | PD_SH5 | PU_SH6 | PD_SH6 | PU_SH7 | PD_SH7 | PU_SH8 | PD_SH8 |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PU_SH5 | R/W | 0b | Half-bridge 5 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
6 | PD_SH5 | R/W | 0b | Half-bridge 5 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
5 | PU_SH6 | R/W | 0b | Half-bridge 6 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
4 | PD_SH6 | R/W | 0b | Half-bridge 6 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
3 | PU_SH7 | R/W | 0b | Half-bridge 7 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
2 | PD_SH7 | R/W | 0b | Half-bridge 7 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
1 | PU_SH8 | R/W | 0b | Half-bridge 8 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
0 | PD_SH8 | R/W | 0b | Half-bridge 8 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
UVOV_CTRL is shown in Figure 8-37 and described in Table 8-45.
Return to the Summary Table.
Control register to set the undervoltage and overvoltage monitor configurations.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PVDD_UV_MODE | PVDD_OV_MODE | PVDD_OV_DG | PVDD_OV_LVL | VCP_UV_MODE | VCP_UV_LVL | ||
R/W-0b | R/W-00b | R/W-10b | R/W-1b | R/W-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PVDD_UV_MODE | R/W | 0b | PVDD supply undervoltage monitor mode.
0b = Latched fault. 1b = Automatic recovery. |
6-5 | PVDD_OV_MODE | R/W | 00b | PVDD supply overvoltage monitor mode.
00b = Latched fault. 01b = Automatic recovery. 10b = Warning report only. 11b = Disabled. |
4-3 | PVDD_OV_DG | R/W | 10b | PVDD supply overvoltage monitor deglitch time.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
2 | PVDD_OV_LVL | R/W | 1b | PVDD supply overvoltage monitor threshold.
0b = 21.5 V 1b = 28.5 V |
1 | VCP_UV_MODE | R/W | 0b | VCP charge pump undervoltage monitor mode.
0b = Latched fault. 1b = Automatic recovery. |
0 | VCP_UV_LVL | R/W | 0b | VCP charge pump undervoltage monitor threshold.
0b = 4.75 V 1b = 6.25 V |
CSA_CTRL1 is shown in Figure 8-38 and described in Table 8-46.
Return to the Summary Table.
Control register for gain and reference voltage for shunt amplifier 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_DIV_1 | CSA_GAIN_1 | CSA_DIV_2 | CSA_GAIN_2 | |||
R-00b | R/W-0b | R/W-01b | R/W-0b | R/W-01b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5 | CSA_DIV_1 | R/W | 0b | Current shunt amplifier 1 reference voltage divider.
0b = AREF / 2 1b = AREF / 8 |
4-3 | CSA_GAIN_1 | R/W | 01b | Current shunt amplifier 1 gain setting.
00b = 10 V/V 01b = 20 V/V 10b = 40 V/V 11b = 80 V/V |
2 | CSA_DIV_2 | R/W | 0b | Current shunt amplifier 2 reference voltage divider.
0b = AREF / 2 1b = AREF / 8 |
1-0 | CSA_GAIN_2 | R/W | 01b | Current shunt amplifier 2 gain setting.
00b = 10 V/V 01b = 20 V/V 10b = 40 V/V 11b = 80 V/V |
CSA_CTRL2 is shown in Figure 8-39 and described in Table 8-47.
Return to the Summary Table.
Control register for shunt amplifier 1 blanking configuration.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_BLK_SEL_1 | CSA_BLK_LVL_1 | |||||
R-00b | R/W-000b | R/W-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | CSA_BLK_SEL_1 | R/W | 000b | Current shunt amplifier 1 blanking trigger source.
000b = Half-bridge 1 001b = Half-bridge 2 010b = Half-bridge 3 011b = Half-bridge 4 100b = Half-bridge 5 101b = Half-bridge 6 110b = Half-bridge 7 111b = Half-bridge 8 |
2-0 | CSA_BLK_LVL_1 | R/W | 000b | Current shunt amplifier 1 blanking time. % of tDRV.
000b = 0 %, Disabled 001b = 25 % 010b = 37.5 % 011b = 50 % 100b = 62.5 % 101b = 75 % 110b = 87.5 % 111b = 100 % |
CSA_CTRL3 is shown in Figure 8-40 and described in Table 8-48.
Return to the Summary Table.
Control register for shunt amplifier 2 blanking configuration.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_BLK_SEL_2 | CSA_BLK_LVL_2 | |||||
R-00b | R/W-100b | R/W-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | CSA_BLK_SEL_2 | R/W | 100b | Current shunt amplifier 2 blanking trigger source.
000b = Half-bridge 1 001b = Half-bridge 2 010b = Half-bridge 3 011b = Half-bridge 4 100b = Half-bridge 5 101b = Half-bridge 6 110b = Half-bridge 7 111b = Half-bridge 8 |
2-0 | CSA_BLK_LVL_2 | R/W | 000b | Current shunt amplifier 2 blanking time. % of tDRV.
000b = 0 %, Disabled 001b = 25 % 010b = 37.5 % 011b = 50 % 100b = 62.5 % 101b = 75 % 110b = 87.5 % 111b = 100 % |