SLVSEA2D August 2020 – April 2024 DRV8714-Q1 , DRV8718-Q1
PRODMIX
Table 8-81 lists the DRV8714-Q1_CONTROL registers. All register offset addresses not listed in Table 8-81 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Section |
---|---|---|---|
7h | IC_CTRL1 | Device general function control register 1 | Go |
8h | IC_CTRL2 | Device general function control register 2 | Go |
9h | BRG_CTRL1 | Half-bridge 1-4 output state control | Go |
Ah | BRG_CTRL2 | H-bridge 1/2 and 3/4 control | Go |
Bh | PWM_CTRL1 | Half-bridge 1-4 PWM mapping control | Go |
Ch | PWM_CTRL2 | H-bridge 1/2 and 3/4 configuration | Go |
Dh | PWM_CTRL3 | Half-bridge 1-4 high-side or low-side drive control | Go |
Eh | PWM_CTRL4 | Half-bridge 1-4 freewheeling configuration | Go |
Fh | IDRV_CTRL1 | Half-bridge 1 gate drive source/sink current | Go |
10h | IDRV_CTRL2 | Half-bridge 2 gate drive source/sink current | Go |
11h | IDRV_CTRL3 | Half-bridge 3 gate drive source/sink current | Go |
12h | IDRV_CTRL4 | Half-bridge 4 gate drive source/sink current | Go |
17h | IDRV_CTRL9 | Half-bridge 1-4 gate drive low current control | Go |
18h | DRV_CTRL1 | Gate driver VGS and VDS monitor configuration | Go |
19h | DRV_CTRL2 | Half-bridge 1 and 2 VGS and VDS tDRV configuration | Go |
1Ah | DRV_CTRL3 | Half-bridge 3 and 4 VGS and VDS tDRV configuration | Go |
1Bh | DRV_CTRL4 | Half-bridge 1-4 VGS tDEAD_D configuration | Go |
1Ch | DRV_CTRL5 | Half-bridge 1-4 VDS tDS_DG configuration | Go |
1Dh | DRV_CTRL6 | Half-bridge 1-4 VDS fault pulldown current configuration | Go |
1Fh | VDS_CTRL1 | Half-bridge 1 and 2 VDS overcurrent threshold | Go |
20h | VDS_CTRL2 | Half-bridge 3 and 4 VDS overcurrent threshold | Go |
23h | OLSC_CTRL1 | Half-bridge 1-4 offline diagnostic control | Go |
25h | UVOV_CTRL | Undervoltage and overvoltage monitor configuration. | Go |
26h | CSA_CTRL1 | Shunt amplifier 1 and 2 configuration | Go |
27h | CSA_CTRL2 | Shunt amplifier 1 blanking configuration | Go |
28h | CSA_CTRL3 | Shunt amplifier 2 blanking configuration | Go |
Complex bit access types are encoded to fit into small table cells. Table 8-82 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
- n | Value after reset or the default value |
IC_CTRL1 is shown in Figure 8-67 and described in Table 8-83.
Return to the Summary Table.
Control register for driver and diagnostic enable, PWM control mode, SPI lock, and clear fault command.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EN_DRV | EN_OLSC | BRG_MODE | LOCK | CLR_FLT | |||
R/W-0b | R/W-0b | R/W-00b | R/W-011b | R/W-0b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | EN_DRV | R/W | 0b | Enable gate drivers.
0b = Gate driver output disabled and passive pulldowns enabled. 1b = Gate driver outputs enabled. |
6 | EN_OLSC | R/W | 0b | Enable offline open load and short circuit diagnostic.
0b = Disabled. 1b = VDS monitors set into real-time voltage monitor mode and offline diagnostics current sources enabled. |
5-4 | BRG_MODE | R/W | 00b | Bridge PWM control mode.
00b = Independent Half-Bridge 01b = H-Bridge PH/EN 10b = H-Bridge PWM 11b = Solenoid Control |
3-1 | LOCK | R/W | 011b | Lock and unlock the control registers. Bit settings not listed have no effect.
011b = Unlock all control registers. 110b = Lock the control registers by ignoring further writes except to the LOCK register. |
0 | CLR_FLT | R/W | 0b | Clear latched fault status information.
0b = Default state. 1b = Clear latched fault bits, resets to 0b after completion. Will also clear SPI fault and watchdog fault status. |
IC_CTRL2 is shown in Figure 8-68 and described in Table 8-84.
Return to the Summary Table.
Control register for pin mode, charge pump mode, and watchdog.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIS_SSC | DRVOFF_nFLT | CP_MODE | WD_EN | WD_FLT_M | WD_WIN | WD_RST | |
R/W-0b | R/W-0b | R/W-00b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DIS_SSC | R/W | 0b | Spread spectrum clocking
0b = Enabled. 1b = Disabled. |
6 | DRVOFF_nFLT | R/W | 0b | Sets DRVOFF/nFLT multi-function pin mode.
0b = Pin functions as DRVOFF global driver disable. 1b = Pin functions as nFLT open-drain fault interrupt output. |
5-4 | CP_MODE | R/W | 00b | Charge pump operating mode.
00b = Automatic switch between tripler and doubler mode. 01b = Always doubler mode. 10b = Always tripler mode. 11b = RSVD |
3 | WD_EN | R/W | 0b | Watchdog timer enable.
0b = Watchdog timer disabled. 1b = Watchdog dog timer enabled. |
2 | WD_FLT_M | R/W | 0b | Watchdog fault mode. Watchdog fault is cleared by CLR_FLT.
0b = Watchdog fault is reported to WD_FLT and WARN register bits. Gate drivers remain enabled and nFAULT is not asserted. 1b = Watchdog fault is reported to WD_FLT, FAULT register bits, and nFAULT pin. Gate drivers are disabled in response to watchdog fault. |
1 | WD_WIN | R/W | 1b | Watchdog timer window.
0b = 4 to 40 ms 1b = 10 to 100 ms |
0 | WD_RST | R/W | 0b | Watchdog restart. 0b by default after power up. Invert this bit to restart the watchdog timer. After written, the bit will reflect the new inverted value. |
BRG_CTRL1 is shown in Figure 8-69 and described in Table 8-85.
Return to the Summary Table.
Control register to set the output state for half-bridges 1-4 in independent half-bridge mode (BRG_MODE = 00b).
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_CTRL | HB2_CTRL | HB3_CTRL | HB4_CTRL | ||||
R/W-00b | R/W-00b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HB1_CTRL | R/W | 00b | Half-bridge 1 output state control.
00b = High impedance (HI-Z). GH1 and GL1 pulldown. 01b = Drive low-side (LO). GH1 pulldown and GL1 pullup. 10b = Drive high-side (HI). GH1 pullup and GL1 pulldown. 11b = Input PWM control. HB1_PWM, HB1_HL, and HB1_FW. |
5-4 | HB2_CTRL | R/W | 00b | Half-bridge 2 output state control.
00b = High impedance (HI-Z). GH2 and GL2 pulldown. 01b = Drive low-side (LO). GH2 pulldown and GL2 pullup. 10b = Drive high-side (HI). GH2 pullup and GL2 pulldown. 11b = Input PWM control. HB2_PWM, HB2_HL, and HB2_FW. |
3-2 | HB3_CTRL | R/W | 00b | Half-bridge 3 output state control.
00b = High impedance (HI-Z). GH3 and GL3 pulldown. 01b = Drive low-side (LO). GH3 pulldown and GL3 pullup. 10b = Drive high-side (HI). GH3 pullup and GL3 pulldown. 11b = Input PWM control. HB3_PWM, HB3_HL, and HB3_FW. |
1-0 | HB4_CTRL | R/W | 00b | Half-bridge 4 output state control.
00b = High impedance (HI-Z). GH4 and GL4 pulldown. 01b = Drive low-side (LO). GH4 pulldown and GL4 pullup. 10b = Drive high-side (HI). GH4 pullup and GL4 pulldown. 11b = Input PWM control. HB4_PWM, HB4_HL, and HB4_FW. |
BRG_CTRL2 is shown in Figure 8-70 and described in Table 8-86.
Return to the Summary Table.
Control register to set the output state for H-bridges 1/2 and 3/4 in H-bridge control modes (BRG_MODE = 01b, 10b, or 11b)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
S_IN1/EN1 | S_IN2/PH1 | HIZ1 | RESERVED | S_IN3/EN2 | S_IN4/PH2 | HIZ2 | RESERVED |
R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-0b | R/W-0b | R/W-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | S_IN1/EN1 | R/W | 0b | Control bit for IN1/EN1 input signal. Enabled through IN1/EN1_MODE bit. |
6 | S_IN2/PH1 | R/W | 0b | Control bit for IN2/PH1 input signal. Enabled through IN2/PH1_MODE bit. |
5 | HIZ1 | R/W | 0b | Control bit for HIZ1 input signal.
0b = Outputs follow IN1/EN1 and IN2/PH1 signals. 1b = Gate drivers pulldowns are enabled. Half-bridges 1 and 2 Hi-Z |
4 | RESERVED | R | 0b | Reserved |
3 | S_IN3/EN2 | R/W | 0b | Control bit for IN3/EN2 input signal. Enabled through IN3/EN2_MODE bit. |
2 | S_IN4/PH2 | R/W | 0b | Control bit for IN4/PH2 input signal. Enabled through IN4/PH2_MODE bit. |
1 | HIZ2 | R/W | 0b | Control bit for HIZ2 input signal.
0b = Outputs follow IN3/EN2 and IN4/PH2 signals. 1b = Gate drivers pulldowns are enabled. Half-bridges 3 and 4 Hi-Z |
0 | RESERVED | R | 0b | Reserved |
PWM_CTRL1 is shown in Figure 8-71 and described in Table 8-87.
Return to the Summary Table.
Control register to map the input PWM source for half-bridges 1-4 in independent half-bridge mode (BRG_MODE = 00b).
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_PWM | HB2_PWM | HB3_PWM | HB4_PWM | ||||
R/W-00b | R/W-00b | R/W-01b | R/W-01b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | HB1_PWM | R/W | 00b | Configure PWM input source for half-bridge 1.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
5-4 | HB2_PWM | R/W | 00b | Configure PWM input source for half-bridge 2.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
3-2 | HB3_PWM | R/W | 01b | Configure PWM input source for half-bridge 3.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
1-0 | HB4_PWM | R/W | 01b | Configure PWM input source for half-bridge 4.
00b = IN1 01b = IN2 10b = IN3 11b = IN4 |
PWM_CTRL2 is shown in Figure 8-72 and described in Table 8-88.
Return to the Summary Table.
Control register to configure the PWM method for H-bridges 1/2 and 3/4 in H-bridge control modes (BRG_MODE = 01b, 10b, or 11b)
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN1/EN1_MODE | IN2/PH1_MODE | FW1 | RESERVED | IN3/EN2_MODE | IN4/PH2_MODE | FW2 | RESERVED |
R/W-0b | R/W-0b | R/W-0b | R-0b | R/W-0b | R/W-0b | R/W-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IN1/EN1_MODE | R/W | 0b | IN1/EN1 control mode.
0b = IN1/EN1 signal is sourced from the IN1/EN1 pin. 1b = IN1/EN1 signal is sourced from the S_IN1/EN1 bit. |
6 | IN2/PH1_MODE | R/W | 0b | IN2/PH1 control mode.
0b = IN2/PH1 signal is sourced from the IN2/PH1 pin. 1b = IN2/PH1 signal is sourced from the S_IN2/PH1 bit. |
5 | FW1 | R/W | 0b | H-bridge 1 control freewheeling setting.
0b = Low-side freewheeling. 1b = High-side freewheeling. |
4 | RESERVED | R | 0b | Reserved |
3 | IN3/EN2_MODE | R/W | 0b | IN3/EN2 control mode.
0b = IN3/EN2 signal is sourced from the IN3/EN2 pin. 1b = IN3/EN2 signal is sourced from the S_IN3/EN2 bit. |
2 | IN4/PH2_MODE | R/W | 0b | IN4/PH2 control mode.
0b = IN4/PH2 signal is sourced from the IN4/PH2 pin. 1b = IN4/PH2 signal is sourced from the S_IN4/PH2 bit. |
1 | FW2 | R/W | 0b | H-bridge 2 control freewheeling setting.
0b = Low-side freewheeling. 1b = High-side freewheeling. |
0 | RESERVED | R | 0b | Reserved |
PWM_CTRL3 is shown in Figure 8-73 and described in Table 8-89.
Return to the Summary Table.
Control register to set the PWM drive MOSFET (high or low) for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_HL | HB2_HL | HB3_HL | HB4_HL | RESERVED | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | HB1_HL | R/W | 0b | Map half-bridge 1 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
6 | HB2_HL | R/W | 0b | Map half-bridge 2 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
5 | HB3_HL | R/W | 0b | Map half-bridge 3 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
4 | HB4_HL | R/W | 0b | Map half-bridge 4 PWM to high-side or low-side gate driver.
0b = Set high-side as drive MOSFET. 1b = Set low-side as drive MOSFET. |
3-0 | RESERVED | R | 0000b | Reserved |
PWM_CTRL4 is shown in Figure 8-74 and described in Table 8-90.
Return to the Summary Table.
Control register to set the PWM freewheeling mode for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
HB1_FW | HB2_FW | HB3_FW | HB4_FW | RESERVED | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | HB1_FW | R/W | 0b | Configure freewheeling setting for half-bridge 1.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
6 | HB2_FW | R/W | 0b | Configure freewheeling setting for half-bridge 2.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
5 | HB3_FW | R/W | 0b | Configure freewheeling setting for half-bridge 3.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
4 | HB4_FW | R/W | 0b | Configure freewheeling setting for half-bridge 4.
0b = Active. Generate inverted PWM internally. 1b = Passive. Rely on freewheeling diode. |
3-0 | RESERVED | R | 0000b | Reserved |
IDRV_CTRL1 is shown in Figure 8-75 and described in Table 8-91.
Return to the Summary Table.
Control register to configure the source and sink current for the half-bridge 1 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_1 | IDRVN_1 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_1 | R/W | 1111b | Half-bridge 1 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO1).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_1 | R/W | 1111b | Half-bridge 1 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO1).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL2 is shown in Figure 8-76 and described in Table 8-92.
Return to the Summary Table.
Control register to configure the source and sink current for the half-bridge 2 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_2 | IDRVN_2 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_2 | R/W | 1111b | Half-bridge 2 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO2).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_2 | R/W | 1111b | Half-bridge 2 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO2).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL3 is shown in Figure 8-77 and described in Table 8-93.
Return to the Summary Table.
Control register to configure the source and sink current for the half-bridge 3 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_3 | IDRVN_3 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_3 | R/W | 1111b | Half-bridge 3 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO3).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_3 | R/W | 1111b | Half-bridge 3 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO3).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL4 is shown in Figure 8-78 and described in Table 8-94.
Return to the Summary Table.
Control register to configure the source and sink current for the half-bridge 4 high-side and low-side gate drivers.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRVP_4 | IDRVN_4 | ||||||
R/W-1111b | R/W-1111b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | IDRVP_4 | R/W | 1111b | Half-bridge 4 peak source pull up current. Alternative low current value in parenthesis (IDRV_LO4).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
3-0 | IDRVN_4 | R/W | 1111b | Half-bridge 4 peak sink pull down current. Alternative low current value in parenthesis (IDRV_LO4).
0000b = 0.5 mA (50 µA) 0001b = 1 mA (110 µA) 0010b = 2 mA (170 µA) 0011b = 3 mA (230 µA) 0100b = 4 mA (290 µA) 0101b = 5 mA (350 µA) 0110b = 6 mA (410 µA) 0111b = 7 mA (600 µA) 1000b = 8 mA (725 µA) 1001b = 12 mA (850 µA) 1010b = 16 mA (1 mA) 1011b = 20 mA (1.2 mA) 1100b = 24 mA (1.4 mA) 1101b = 31 mA (1.6 mA) 1110b = 48 mA (1.8 mA) 1111b = 62 mA (2.3 mA) |
IDRV_CTRL9 is shown in Figure 8-79 and described in Table 8-95.
Return to the Summary Table.
Control register to enable ultra-low source and sink current settings for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IDRV_LO1 | IDRV_LO2 | IDRV_LO3 | IDRV_LO4 | RESERVED | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0000b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | IDRV_LO1 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 1.
0b = IDRVP_1 and IDRVN_1 utilize standard values. 1b = IDRVP_1 and IDRVN_1 utilize low current values. |
6 | IDRV_LO2 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 2.
0b = IDRVP_2 and IDRVN_2 utilize standard values. 1b = IDRVP_2 and IDRVN_2 utilize low current values. |
5 | IDRV_LO3 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 3.
0b = IDRVP_3 and IDRVN_3 utilize standard values. 1b = IDRVP_3 and IDRVN_3 utilize low current values. |
4 | IDRV_LO4 | R/W | 0b | Enable low current IDRVN and IDRVP mode for half-bridge 4.
0b = IDRVP_4 and IDRVN_4 utilize standard values. 1b = IDRVP_4 and IDRVN_4 utilize low current values. |
3-0 | RESERVED | R | 0000b | Reserved |
DRV_CTRL1 is shown in Figure 8-80 and described in Table 8-96.
Return to the Summary Table.
Control register to set the VGS and VDS monitor operating modes and configurations.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VGS_MODE | VGS_IND | VGS_LVL | VGS_HS_DIS | VDS_MODE | VDS_IND | ||
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-00b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VGS_MODE | R/W | 00b | VGS gate fault monitor mode for half-bridges 1-4.
00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled. |
5 | VGS_IND | R/W | 0b | VGS fault independent shutdown mode configuration.
0b = Disabled. VGS fault will shut down all half-bridge drivers. 1b = Enabled. VGS gate fault will only shutdown the associated half-bridge or H-bridge driver depending on BRG_MODE. |
4 | VGS_LVL | R/W | 0b | VGS threshold comparator level for dead-time handshake and VGS fault monitor for half-bridge drivers.
0b = 1.4 V 1b = 1 V |
3 | VGS_HS_DIS | R/W | 0b | VGS dead-time handshake monitor disable.
0b = 0x0 1b = Disabled. Half-bridge transition is based only on TDRIVE and programmable digital dead-time delays. |
2-1 | VDS_MODE | R/W | 00b | VDS overcurrent monitor mode for half-bridges 1-4.
00b = Latched fault. 01b = Cycle by cycle. 10b = Warning report only. 11b = Disabled. |
0 | VDS_IND | R/W | 0b | VDS fault independent shutdown mode configuration.
0b = Disabled. VDS fault will shut down all half-bridge drivers. 1b = Enabled. VDS gate fault will only shutdown the associated half-bridge or H-bridge drivers depending on BRG_MODE. |
DRV_CTRL2 is shown in Figure 8-81 and described in Table 8-97.
Return to the Summary Table.
Control register to set tDRV, the VGS drive and VDS monitor blanking time for half-bridges 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VGS_TDRV_1 | VGS_TDRV_2 | |||||
R-00b | R/W-010b | R/W-010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | VGS_TDRV_1 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 1.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
2-0 | VGS_TDRV_2 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 2.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
DRV_CTRL3 is shown in Figure 8-82 and described in Table 8-98.
Return to the Summary Table.
Control register to set tDRV, the VGS drive and VDS monitor blanking time for half-bridges 3 and 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VGS_TDRV_3 | VGS_TDRV_4 | |||||
R-00b | R/W-010b | R/W-010b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | VGS_TDRV_3 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 3.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
2-0 | VGS_TDRV_4 | R/W | 010b | VGS drive and VDS monitor blanking time for half-bridge 4.
000b = 2 µs 001b = 4 µs 010b = 8 µs 011b = 12 µs 100b = 16 µs 101b = 24 µs 110b = 32 µs 111b = 96 µs |
DRV_CTRL4 is shown in Figure 8-83 and described in Table 8-99.
Return to the Summary Table.
Control register to set VGS tDEAD_D, additional digital dead-time insertion for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VGS_TDEAD_1 | VGS_TDEAD_2 | VGS_TDEAD_3 | VGS_TDEAD_4 | ||||
R/W-00b | R/W-00b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VGS_TDEAD_1 | R/W | 00b | Insertable digital dead-time for half-bridge 1.
00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
5-4 | VGS_TDEAD_2 | R/W | 00b | Insertable digital dead-time for half-bridge 2. 00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
3-2 | VGS_TDEAD_3 | R/W | 00b | Insertable digital dead-time for half-bridge 3.
00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
1-0 | VGS_TDEAD_4 | R/W | 00b | Insertable digital dead-time for half-bridge 4.
00b = 0 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
DRV_CTRL5 is shown in Figure 8-84 and described in Table 8-100.
Return to the Summary Table.
Control register to set VDS tDS_DG, overcurrent monitor deglitch time for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_DG_1 | VDS_DG_2 | VDS_DG_3 | VDS_DG_4 | ||||
R/W-10b | R/W-10b | R/W-10b | R/W-10b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VDS_DG_1 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 1.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
5-4 | VDS_DG_2 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 2.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
3-2 | VDS_DG_3 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 3.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
1-0 | VDS_DG_4 | R/W | 10b | VDS overcurrent monitor deglitch time for half-bridge 4.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
DRV_CTRL6 is shown in Figure 8-85 and described in Table 8-101.
Return to the Summary Table.
Control register to set the gate pulldown current (IDRVN) in response to VDS overcurrent fault for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_IDRVN_1 | VDS_IDRVN_2 | VDS_IDRVN_3 | VDS_IDRVN_4 | ||||
R/W-00b | R/W-00b | R/W-00b | R/W-00b | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VDS_IDRVN_1 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 1.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
5-4 | VDS_IDRVN_2 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 2.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
3-2 | VDS_IDRVN_3 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 3.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
1-0 | VDS_IDRVN_4 | R/W | 00b | IDRVN gate pulldown current after VDS_OCP fault for half-bridge 4.
00b = Programmed IDRVN 01b = 8 mA 10b = 31 mA 11b = 62 mA |
VDS_CTRL1 is shown in Figure 8-86 and described in Table 8-102.
Return to the Summary Table.
Control register to set the VDS overcurrent monitor voltage threshold for half-bridges 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_LVL_1 | VDS_LVL_2 | ||||||
R/W-1101b | R/W-1101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | VDS_LVL_1 | R/W | 1101b | Half-bridge 1 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
3-0 | VDS_LVL_2 | R/W | 1101b | Half-bridge 2 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
VDS_CTRL2 is shown in Figure 8-87 and described in Table 8-103.
Return to the Summary Table.
Control register to set the VDS overcurrent monitor voltage threshold for half-bridges 3 and 4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VDS_LVL_3 | VDS_LVL_4 | ||||||
R/W-1101b | R/W-1101b | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | VDS_LVL_3 | R/W | 1101b | Half-bridge 3 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
3-0 | VDS_LVL_4 | R/W | 1101b | Half-bridge 4 VDS overcurrent monitor threshold.
0000b = 0.06 V 0001b = 0.08 V 0010b = 0.10 V 0011b = 0.12 V 0100b = 0.14 V 0101b = 0.16 V 0110b = 0.18 V 0111b = 0.2 V 1000b = 0.3 V 1001b = 0.4 V 1010b = 0.5 V 1011b = 0.6 V 1100b = 0.7 V 1101b = 1 V 1110b = 1.4 V 1111b = 2 V |
OLSC_CTRL1 is shown in Figure 8-88 and described in Table 8-104.
Return to the Summary Table.
Control register to enable and disable the offline diagnostic current sources for half-bridges 1-4.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PU_SH1 | PD_SH1 | PU_SH2 | PD_SH2 | PU_SH3 | PD_SH3 | PU_SH4 | PD_SH4 |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PU_SH1 | R/W | 0b | Half-bridge 1 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
6 | PD_SH1 | R/W | 0b | Half-bridge 1 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
5 | PU_SH2 | R/W | 0b | Half-bridge 2 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
4 | PD_SH2 | R/W | 0b | Half-bridge 2 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
3 | PU_SH3 | R/W | 0b | Half-bridge 3 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
2 | PD_SH3 | R/W | 0b | Half-bridge 3 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
1 | PU_SH4 | R/W | 0b | Half-bridge 4 pull up diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
0 | PD_SH4 | R/W | 0b | Half-bridge 4 pull down diagnostic current source. Set EN_OLSC = 1b to use.
0b = Disabled. 1b = Enabled. |
UVOV_CTRL is shown in Figure 8-89 and described in Table 8-105.
Return to the Summary Table.
Control register to set the undervoltage and overvoltage monitor configurations.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PVDD_UV_MODE | PVDD_OV_MODE | PVDD_OV_DG | PVDD_OV_LVL | VCP_UV_MODE | VCP_UV_LVL | ||
R/W-0b | R/W-00b | R/W-10b | R/W-1b | R/W-0b | R/W-0b | ||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PVDD_UV_MODE | R/W | 0b | PVDD supply undervoltage monitor mode.
0b = Latched fault. 1b = Automatic recovery. |
6-5 | PVDD_OV_MODE | R/W | 00b | PVDD supply overvoltage monitor mode.
00b = Latched fault. 01b = Automatic recovery. 10b = Warning report only. 11b = Disabled. |
4-3 | PVDD_OV_DG | R/W | 10b | PVDD supply overvoltage monitor deglitch time.
00b = 1 µs 01b = 2 µs 10b = 4 µs 11b = 8 µs |
2 | PVDD_OV_LVL | R/W | 1b | PVDD supply overvoltage monitor threshold.
0b = 21.5 V 1b = 28.5 V |
1 | VCP_UV_MODE | R/W | 0b | VCP charge pump undervoltage monitor mode.
0b = Latched fault. 1b = Automatic recovery. |
0 | VCP_UV_LVL | R/W | 0b | VCP charge pump undervoltage monitor threshold.
0b = 4.75 V 1b = 6.25 V |
CSA_CTRL1 is shown in Figure 8-90 and described in Table 8-106.
Return to the Summary Table.
Control register for gain and reference voltage for shunt amplifier 1 and 2.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_DIV_1 | CSA_GAIN_1 | CSA_DIV_2 | CSA_GAIN_2 | |||
R-00b | R/W-0b | R/W-01b | R/W-0b | R/W-01b | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5 | CSA_DIV_1 | R/W | 0b | Current shunt amplifier 1 reference voltage divider.
0b = AREF / 2 1b = AREF / 8 |
4-3 | CSA_GAIN_1 | R/W | 01b | Current shunt amplifier 1 gain setting.
00b = 10 V/V 01b = 20 V/V 10b = 40 V/V 11b = 80 V/V |
2 | CSA_DIV_2 | R/W | 0b | Current shunt amplifier 2 reference voltage divider.
0b = AREF / 2 1b = AREF / 8 |
1-0 | CSA_GAIN_2 | R/W | 01b | Current shunt amplifier 2 gain setting.
00b = 10 V/V 01b = 20 V/V 10b = 40 V/V 11b = 80 V/V |
CSA_CTRL2 is shown in Figure 8-91 and described in Table 8-107.
Return to the Summary Table.
Control register for shunt amplifier 1 blanking configuration.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_BLK_SEL_1 | CSA_BLK_LVL_1 | |||||
R-00b | R/W-000b | R/W-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | CSA_BLK_SEL_1 | R/W | 000b | Current shunt amplifier 1 blanking trigger source.
000b = Half-bridge 1 001b = Half-bridge 2 010b = Half-bridge 3 011b = Half-bridge 4 100b = Half-bridge 5 101b = Half-bridge 6 110b = Half-bridge 7 111b = Half-bridge 8 |
2-0 | CSA_BLK_LVL_1 | R/W | 000b | Current shunt amplifier 1 blanking time. % of tDRV.
000b = 0 %, Disabled 001b = 25 % 010b = 37.5 % 011b = 50 % 100b = 62.5 % 101b = 75 % 110b = 87.5 % 111b = 100 % |
CSA_CTRL3 is shown in Figure 8-92 and described in Table 8-108.
Return to the Summary Table.
Control register for shunt amplifier 2 blanking configuration.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CSA_BLK_SEL_2 | CSA_BLK_LVL_2 | |||||
R-00b | R/W-100b | R/W-000b | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 00b | Reserved |
5-3 | CSA_BLK_SEL_2 | R/W | 100b | Current shunt amplifier 2 blanking trigger source.
000b = Half-bridge 1 001b = Half-bridge 2 010b = Half-bridge 3 011b = Half-bridge 4 100b = Half-bridge 5 101b = Half-bridge 6 110b = Half-bridge 7 111b = Half-bridge 8 |
2-0 | CSA_BLK_LVL_2 | R/W | 000b | Current shunt amplifier 2 blanking time. % of tDRV.
000b = 0 %, Disabled 001b = 25 % 010b = 37.5 % 011b = 50 % 100b = 62.5 % 101b = 75 % 110b = 87.5 % 111b = 100 % |