SLVSAW4G July   2011  – December 2024 DRV8804

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Thermal Information
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Drivers
      2. 7.3.2 Serial Interface Operation
        1.       Daisy Chain Operation
      3. 7.3.3 nENBL and RESET Operation
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 Overcurrent Protection (OCP)
        2. 7.3.4.2 Thermal Shutdown (TSD)
        3. 7.3.4.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Drive Current
      3. 8.2.3 Application Curves
    3.     Power Supply Recommendations
      1. 8.3.1 Bulk Capacitance
    4. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
      3. 8.3.3 Thermal Considerations
        1. 8.3.3.1 Power Dissipation
        2. 8.3.3.2 Heatsinking
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Community Resources
    3. 9.3 Trademarks
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

When the nENBL pin of the DRV8804 is pulled logic low, the open-drain FET outputs are enabled. Having the device be enabled at logic low allows for the use of long data lines in a high noise environment that do not unintentionally enable the device with coupled noise. The device will still shift data through the SDATIN / SDATOUT lines and SCLK line regardless of the state of the nENBL pin.

Once data has been moved into each of the four shift register lines the LATCH pin can be pulled high to output the state of the four shift registers. Once LATCH is pulled high the state of the four shift registers is placed in a logical AND with the inverse state of the nENBL pin. If the nENBL pin is logic low input and the LATCH pin is logic high the open-drain output of that driver channel will be turned on.

If the device detects that VM has dropped below the UVLO threshold, it will immediately enter a state where all the internal logic is disabled. The device stays in a disabled state until VM rises above the UVLO threshold and all internal logic is then reset. During an Overcurrent Protection (OCP) event the device removes gate drive for one tRETRY interval and the nFAULT pin is driven low. The fault is cleared immediately if RESET is activated or VM is removed and re-applied.