SLRS063C September   2013  – February 2016 DRV8816

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bridge Control
      2. 7.3.2 Charge Pump
      3. 7.3.3 VPROPI
      4. 7.3.4 Protection Circuits
        1. 7.3.4.1 VBB UVLO
        2. 7.3.4.2 VCP UVLO (CPUV)
        3. 7.3.4.3 OCP
        4. 7.3.4.4 OTW
        5. 7.3.4.5 OTS
    4. 7.4 Device Functional Modes
      1. 7.4.1 SENSE
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Power Dissipation
        3. 8.2.2.3 Motor Current Trip Point
        4. 8.2.2.4 Sense Resistor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supervisor
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground
    2. 10.2 Layout Example
    3. 10.3 Thermal Protection
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resource
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VBB Power supply voltage –0.6 40 V
Charge pump positive switching pin (CP2) –0.6 VBB + 7 V
Charge pump negative switching pin (CP1) –0.6 VBB V
Digital pin voltage range (IN1, IN2, EN1, EN2, nSLEEP, nFAULT) –0.3 7 V
VBB to OUTx –0.6 40 V
OUTx to SENSE –0.6 40 V
V(SENSE) Sense voltage (SENSE) (2) –0.5 1.0 V
H-bridge output current (OUT1, OUT2, SENSE) 0 2.8 A
VPROPI pin voltage range (VPROPI) –0.3 3.6 V
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 190 °C
Tstg Storage temperature –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transients of ±1 V for less than 25 ns are acceptable.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Power dissipation and thermal limits must be observed.
MIN MAX UNIT
VBB Power supply voltage 8 38 V
VI Input pin voltage 0 5.5 V
fPWM Applied PWM signal (IN1, IN2, EN1, EN2) 100 kHz
IOUT H-bridge output current 2.8 A
TA Ambient temperature –40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) DRV8816 UNIT
PWP (HTSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance(2) 43.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance(3) 30.8 °C/W
RθJB Junction-to-board thermal resistance(4) 25.3 °C/W
ψJT Junction-to-top characterization parameter(5) 1.1 °C/W
ψJB Junction-to-board characterization parameter(6) 25 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance(7) 5.6 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ JT , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ JA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ JB , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VBB)
VBB VBB operating voltage 8 38 V
IVBB VBB operating supply current ƒPWM < 50 kHz 6 mA
Charge pump on, Outputs disabled 3.2 mA
IVBBQ VBB sleep-mode supply current nSLEEP = 0, TJ = 25°C 10 µA
CONTROL INPUTS (IN1, IN2, EN1, EN2, nSLEEP)
VIL Input logic low voltage IN1, IN2, EN1, EN2 0 0.8 V
VIH Input logic high voltage IN1, IN2, EN1, EN2 2 5.5 V
VIL Input logic low voltage nSLEEP 0 0.8 V
VIH Input logic high voltage nSLEEP 2.2 5.5 V
IIL Input logic low current IN1, IN2, EN2, nSLEEP VIN = 0 V 0 μA
IIH Input logic high current IN1, IN2, EN2, nSLEEP VIN = 5 V 25 μA
IIL Input logic low current EN1 VIN = 0 V 0 μA
IIH Input logic high current EN1 VIN = 5 V 100 μA
RPD Pulldown resistance IN1, IN2, EN2, nSLEEP 200 kΩ
EN1 50
SERIAL AND CONTROL OUTPUT (nFAULT)
VOL Output logic low voltage Isink = 1 mA 0.4 V
DMOS DRIVERS (OUT1, OUT2, SENSE)
RDS(on) Output ON resistance Source driver, IOUT = –2.8 A, TJ = 25°C 0.48 Ω
Source driver, IOUT = –2.8 A, TJ = 125°C 0.74 0.85
Sink driver, IOUT = –2.8 A, TJ = 25°C 0.35
Sink driver, IOUT = –2.8 A, TJ = 125°C 0.52 0.7
VTRIP SENSE trip voltage RSENSE between SENSE and GND 500 mV
Vf Body diode forward voltage Source diode, If = –2.8 A 1.4 V
Sink diode, If = 2.8 A 1.4
tpd OUTx propagation delay From High-Z to High 70 ns
From High-Z to Low 700(2)
From High to High-Z 120
From High to Low 700
From Low to High-Z 350
From Low to High 350
tCOD Crossover delay 500 ns
DAGain VPROPI amplifier gain Sense = 0.1 to 0.4 V 5 V/V
PROTECTION CIRCUITS
VUVLO VBB UVLO VBB rising 6.5 7.5 V
VCPUV VCP UVLO(1) VBB rising; CPUV recovery 12 13.8 V
IOCP Overcurrent protection trip level 3 A
tDEG Overcurrent deglitch time 3.0 µs
tOCP Overcurrent retry time 1.6 ms
TOTW Thermal warning temperature Die temperature Tj 160 °C
TOTW HYS Thermal warning hysteresis Die temperature Tj 15 °C
TOTS Thermal shutdown temperature Die temperature Tj 175 °C
TOTS HYS Thermal shutdown hysteresis Die temperature Tj 15 °C
(1) Whenever VCP is less than VM + 10 V, a CPUV event occurs. This fault will be asserted whenever VBB is below 12 V. Note that the H-bridges will remain enabled until VBB = VUVLO even through nFAULT is pulled low.
(2) If OUT2 is High, the typical time for OUT1 to go from High-Z to Low is 1700 ns.

6.6 Typical Characteristics

DRV8816 C001_SLRS063.png
Figure 1. IVBBQ vs VBB
DRV8816 C003_SLRS063.png
Figure 3. VCP vs VBB
DRV8816 C002_SLRS063.png
Figure 2. RDS(ON) vs VBB (normalized to VBB = 8V)