The DRV8835 provides an integrated motor driver solution for cameras, consumer products, toys, and other low-voltage or battery-powered motion control applications. The device has two H-bridge drivers, and drives two DC motors or one stepper motor, as well as other devices like solenoids. The output driver block for each consists of N-channel power MOSFETs configured as an H-bridge to drive the motor winding. An internal charge pump generates gate drive voltages.
The DRV8835 supplies up to 1.5-A of output current per H-bridge and operates on a motor power supply voltage from 0 V to 11 V, and a device power supply voltage of 2 V to 7 V.
PHASE/ENABLE and IN/IN interfaces are compatible with industry-standard devices.
Internal shutdown functions are provided for overcurrent protection, short circuit protection, undervoltage lockout, and overtemperature.
The DRV8835 is packaged in a tiny 12-pin WSON package (Eco-friendly: RoHS and no Sb/Br).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
DRV8835 | WSON (12) | 2.00 mm × 3.00 mm |
Changes from G Revision (May 2016) to H Revision
Changes from F Revision (April 2016) to G Revision
Changes from E Revision (December 2015) to F Revision
Changes from D Revision (January 2014) to E Revision
Changes from C Revision (September 2013) to D Revision
PIN | I/O(1) | DESCRIPTION | EXTERNAL COMPONENTS OR CONNECTIONS | |
---|---|---|---|---|
NAME | NO. | |||
POWER AND GROUND | ||||
GND, Thermal pad | 6 | — | Device ground | |
VM | 1 | — | Motor supply | Bypass to GND with a 0.1-μF (minimum) ceramic capacitor |
VCC | 12 | — | Device supply | Bypass to GND with a 0.1-μF (minimum) ceramic capacitor |
CONTROL | ||||
MODE | 11 | I | Input mode select | Logic low selects IN/IN mode Logic high selects PH/EN mode Internal pulldown resistor |
AIN1/APHASE | 10 | I | Bridge A input 1/PHASE input | IN/IN mode: Logic high sets AOUT1 high PH/EN mode: Sets direction of H-bridge A Internal pulldown resistor |
AIN2/AENBL | 9 | I | Bridge A input 2/ENABLE input | IN/IN mode: Logic high sets AOUT2 high PH/EN mode: Logic high enables H-bridge A Internal pulldown resistor |
BIN1/BPHASE | 8 | I | Bridge B input 1/PHASE input | IN/IN mode: Logic high sets BOUT1 high PH/EN mode: Sets direction of H-bridge B Internal pulldown resistor |
BIN2/BENBL | 7 | I | Bridge B input 2/ENABLE input | IN/IN mode: Logic high sets BOUT2 high PH/EN mode: Logic high enables H-bridge B Internal pulldown resistor |
OUTPUT | ||||
AOUT1 | 2 | O | Bridge A output 1 | Connect to motor winding A |
AOUT2 | 3 | O | Bridge A output 2 | |
BOUT1 | 4 | O | Bridge B output 1 | Connect to motor winding B |
BOUT2 | 5 | O | Bridge B output 2 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Power supply voltage, VM | –0.3 | 12 | V | ||
Power supply voltage, VCC | –0.3 | 7 | V | ||
Digital input pin voltage | –0.5 | VCC + 0.5 | V | ||
Peak motor drive output current | Internally limited | A | |||
Continuous motor drive output current per H-bridge(3) | –1.5 | 1.5 | A | ||
TJ | Operating junction temperature | –40 | 150 | °C | |
Tstg | Storage temperature | –60 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | Device power supply voltage | 2 | 7 | V | |
VM | Motor power supply voltage | 0 | 11 | V | |
VIN | Logic level input voltage | 0 | VCC | V | |
IOUT | H-bridge output current(1) | 0 | 1.5 | A | |
ƒPWM | Externally applied PWM frequency | 0 | 250 | kHz |
THERMAL METRIC(1) | DRV8835 | UNIT | |
---|---|---|---|
DSS (WSON) | |||
12 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 50.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 58 | °C/W |
RθJB | Junction-to-board thermal resistance | 19.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 20 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.9 | °C/W |
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
1 | t1 | Delay time, xPHASE high to xOUT1 low | 300 | ns | |
2 | t2 | Delay time, xPHASE high to xOUT2 high | 200 | ns | |
3 | t3 | Delay time, xPHASE low to xOUT1 high | 200 | ns | |
4 | t4 | Delay time, xPHASE low to xOUT2 low | 300 | ns | |
5 | t5 | Delay time, xENBL high to xOUTx high | 200 | ns | |
6 | t6 | Delay time, xENBL high to xOUTx low | 300 | ns | |
7 | t7 | Output enable time | 300 | ns | |
8 | t8 | Output disable time | 300 | ns | |
9 | t9 | Delay time, xINx high to xOUTx high | 160 | ns | |
10 | t10 | Delay time, xINx low to xOUTx low | 160 | ns | |
11 | tR | Output rise time | 30 | 188 | ns |
12 | tF | Output fall time | 30 | 188 | ns |
The DRV8835 is an integrated motor-driver solution used for brushed motor control. The device integrates two
H-bridges, and drives two DC motor or one stepper motor. The output driver block for each H-bridge consists of
N-channel power MOSFETs. An internal charge pump generates the gate drive voltages. Protection features include overcurrent protection, short circuit protection, undervoltage lockout, and overtemperature protection.
The bridges connect in parallel for additional current capability.
The DRV8835 allows separation of the motor voltage and logic voltage if desired. If VM and VCC are less than
7 V, the two voltages can be connected.
The mode pin allow selection of either a PHASE/ENABLE or IN/IN interface.
The DRV8835 is fully protected against undervoltage, overcurrent, and overtemperature events.
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this analog current limit persists for longer than the OCP time, all FETs in the H-bridge disable. After approximately
1 ms, the bridge re-enable automatically.
Overcurrent conditions on both high-side and low-side devices; a short to ground, supply, or across the motor winding result in an overcurrent shutdown.
If the die temperature exceeds safe limits, all FETs in the H-bridge disable. Operation automatically resumes once the die temperature falls to a safe level.
If at any time the voltage on the VCC pins falls below the undervoltage lockout threshold voltage, all circuitry in the device disable, and internal logic resets. Operation resumes when VCC rises above the UVLO threshold.
FAULT | CONDITION | ERROR REPORT | H-BRIDGE | INTERNAL CIRCUITS | RECOVERY |
---|---|---|---|---|---|
VCC undervoltage (UVLO) | VCC < VUVLO | None | Disabled | Disabled | VCC > VUVLO |
Overcurrent (OCP) | IOUT > IOCP | None | Disabled | Operating | tOCR |
Thermal Shutdown (TSD) | TJ > TTSD | None | Disabled | Operating | TJ < TTSD – THYS |
The DRV8835 is active when the VCC is set to a logic high. When in sleep mode, the H-bridge FETs are disabled (HIGH-Z).
OPERATING MODE | CONDITION | H-BRIDGE | INTERNAL CIRCUITS |
---|---|---|---|
Operating | nSLEEP high | Operating | Operating |
Sleep mode | nSLEEP low | Disabled | Disabled |
Fault encountered | Any fault condition met | Disabled | See Table 1 |
Two control modes are available in the DRV8835: IN/IN mode, and PHASE/ENABLE mode. IN/IN mode is selected if the MODE pin is driven low or left unconnected; PHASE/ENABLE mode is selected if the MODE pin is driven to logic high. Table 3 and Table 4 show the logic for these modes.
MODE | xIN1 | xIN2 | xOUT1 | xOUT2 | FUNCTION (DC MOTOR) |
---|---|---|---|---|---|
0 | 0 | 0 | Z | Z | Coast |
0 | 0 | 1 | L | H | Reverse |
0 | 1 | 0 | H | L | Forward |
0 | 1 | 1 | L | L | Brake |
MODE | xENABLE | xPHASE | xOUT1 | xOUT2 | FUNCTION (DC MOTOR) |
---|---|---|---|---|---|
1 | 0 | X | L | L | Brake |
1 | 1 | 1 | L | H | Reverse |
1 | 1 | 0 | H | L | Forward |
If the VCC pin reaches 0 V, the DRV8835 enters a low-power sleep mode. In this state all unnecessary internal circuitry powers down. For minimum supply current, all inputs should be low (0 V) during sleep mode.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The DRV8835 is used in one or two motor control applications. Configure the DRV8835 in parallel to provide double the current to one motor. The following design procedure can be used to configure the DRV8835 in a brushed motor application.
The two H-bridges in the DRV8835 connect in parallel for double the current of a single H-bridge. Figure 6 shows the connections.
Table 5 lists the design requirements.
DESIGN PARAMETER | REFERENCE | VALUE |
---|---|---|
Motor voltage | VCC | 4 V |
Motor RMS current | IRMS | 0.3 A |
Motor startup current | ISTART | 0.6 A |
Motor current trip point | ILIMIT | 0.5 A |
The appropriate motor voltage depends on the ratings of the motor selected and the desired RPM. A higher voltage spins a brushed DC motor faster with the same PWM duty cycle applied to the power FETs. A higher voltage also increases the rate of current change through the inductive motor windings.
When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power.
The following scope captures motor startup as VCC ramps from 0 V to 6 V. Channel 1 is VCC, Channel 2 is VM, and Channel 4 is the motor current of an unloaded motor during startup. The motor used is a NMB Technologies Corporation, PPN7PA12C1. As VCC and VM ramp, the current in the motor increases until the motor speed builds up. The motor current then reduces for normal operation.
Inputs are set as follows:
Channel 1: VM | IN1 = Logic High | |
Channel 2: VCC | IN2 = Logic Low | Motor used: NMB Technologies Corporation, PPN7PA12C1 |
Channel 4: Motor current |
The appropriate local bulk capacitance is an important factor in motor drive system design. More bulk capacitance is generally beneficial, but may increase costs and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
There is a weak pulldown resistor (approximately 100 kΩ) to ground on the input pins.
VCC and VM may be applied and removed in any order. When VCC is removed, the device enters a low power state and draws very little current from VM. To minimize current draw, keep the input pins at 0 V during sleep mode.
The VM voltage supply does not have any undervoltage lockout protection (UVLO), so as long as VCC > 1.8 V, the internal device logic remains active. This means that the VM pin voltage may drop to 0 V, however, the load may not be sufficiently driven at low-VM voltages.
The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1 μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace.
The VM pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value of 0.1 μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace. The VM pin must bypass to ground using an appropriate bulk capacitor. This component can be an electrolytic and should be located close to the DRV8835.
The DRV8835 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately 150°C, the device disables until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or excessively high ambient temperature.
Power dissipation in the DRV8835 is dominated by the power dissipated in the output FET resistance, or RDS(on). Average power dissipation when running both H-bridges can be roughly estimated by Equation 1:
where
The maximum amount of power dissipated in the device is dependent on ambient temperature and heatsinking.
NOTE
RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Consider this increase when sizing the heatsink.
The power dissipation of the DRV8835 is a function of RMS motor current and the resistance of each FET (RDS(ON)), see Equation 2.
For this example, the ambient temperature is 35°C, and the junction temperature reaches 65°C. At 65°C, the sum of RDS(on) is about 1 Ω. With an example motor current of 0.8 A, the dissipated power in the form of heat will be 0.8 A2 × 1 Ω = 0.64 W.
The temperature that the DRV8835 reaches depends on the thermal resistance to the air and PCB. It is important to solder the device thermal pad to the PCB ground plane, with vias to the top and bottom board layers, in order dissipate heat into the PCB and reduce the device temperature. In the example used here, the DRV8835 had an effective thermal resistance RθJA of 47°C/W, and as shown in Equation 3.
The package uses an exposed pad to remove heat from the device. For proper operation, this pad must thermally connect to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.
For more PCB design details, refer to QFN/SON PCB Attachment and AN-1187 Leadless Leadframe Package (LLP), available at www.ti.com.
In general, the more copper area that is provided, the more power can be dissipated.