SLVSB17D March   2012  – April 2016 DRV8836

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sleep Mode
      2. 7.3.2 Power Supplies and Input Pins
      3. 7.3.3 Protection Circuits
        1. 7.3.3.1 Overcurrent Protection (OCP)
        2. 7.3.3.2 Thermal Shutdown (TSD)
        3. 7.3.3.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bridge Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Low-Power Operation
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
      2. 10.3.2 Heatsinking
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DSS Package
12-Pin WSON
Top View
DRV8836 po_lvsb17.gif

Pin Functions

PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS
OR CONNECTIONS
NAME NO.
POWER AND GROUND
GND, Thermal pad 6 — Device ground
VCC 1 — Device and motor supply Bypass to GND with a 0.1-μF (minimum) ceramic capacitor
CONTROL
AIN1/APHASE 10 I Bridge A input 1/PHASE input IN/IN mode: Logic high sets AOUT1 high
PH/EN mode: Sets direction of H-bridge A
Internal pulldown resistor
AIN2/AENBL 9 I Bridge A input 2/ENABLE input IN/IN mode: Logic high sets AOUT2 high
PH/EN mode: Logic high enables H-bridge A
Internal pulldown resistor
BIN1/BPHASE 8 I Bridge B input 1/PHASE input IN/IN mode: Logic high sets BOUT1 high
PH/EN mode: Sets direction of H-bridge B
Internal pulldown resistor
BIN2/BENBL 7 I Bridge B input 2/ENABLE input IN/IN mode: Logic high sets BOUT2 high
PH/EN mode: Logic high enables H-bridge B
Internal pulldown resistor
MODE 11 I Input mode select Logic low selects IN/IN mode
Logic high selects PH/EN mode
Internal pulldown resistor
nSLEEP 12 I Sleep input Active low places part in low-power sleep state
Internal pulldown resistor
OUTPUT
AOUT1 2 O Bridge A output 1 Connect to motor winding A
AOUT2 3 O Bridge A output 2
BOUT1 4 O Bridge B output 1 Connect to motor winding B
BOUT2 5 O Bridge B output 2
(1) Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output.