7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)(2)
|
MIN |
MAX |
UNIT |
V(VM) |
Power supply voltage |
–0.3 |
47 |
V |
|
Digital pin voltage |
–0.5 |
7 |
V |
V(VREF) |
Input voltage |
–0.3 |
4 |
V |
|
ISEN pins |
–0.3 |
0.8 |
V |
|
Peak motor drive output current, t < 1 μs |
Internally limited |
A |
|
Continuous motor drive output current(3) |
|
5 |
A |
|
Continuous total power dissipation |
See Thermal Information |
|
TJ |
Operating virtual junction temperature range |
–55 |
150 |
°C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.
7.2 Handling Ratings
|
MIN |
MAX |
UNIT |
Tstg |
Storage temperature range |
–60 |
150 |
°C |
V(ESD)(1) |
Electrostatic discharge |
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) |
–500 |
4000 |
V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(3) |
–250 |
1500 |
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into the device.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1 kV may actually have higher performance.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
|
MIN |
NOM |
MAX |
UNIT |
VM |
Motor power supply voltage range(1) |
8.2 |
|
45 |
V |
V(VREF) |
VREF input voltage(2) |
1 |
|
3.5 |
V |
IV3P3 |
V3P3OUT load current |
0 |
|
1 |
mA |
ƒPWM |
Externally applied PWM frequency |
0 |
|
100 |
kHz |
TJ |
Operating virtual junction temperature range |
–55 |
|
125 |
°C |
(1) All VM pins must be connected to the same supply voltage.
(2) Operational at V(VREF) between 0 and 1 V, but accuracy is degraded.
7.4 Thermal Information
THERMAL METRIC(1) |
DRV8842-EP |
UNIT |
PWP |
28 PINS |
RθJA |
Junction-to-ambient thermal resistance(2) |
35.6 |
°C/W |
RθJC(top) |
Junction-to-case (top) thermal resistance(3) |
15.6 |
RθJB |
Junction-to-board thermal resistance(4) |
13.5 |
ψJT |
Junction-to-top characterization parameter(5) |
0.4 |
ψJB |
Junction-to-board characterization parameter(6) |
13.3 |
RθJC(bot) |
Junction-to-case (bottom) thermal resistance(7) |
1.4 |
(1) For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics application report,
SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.